ADVANCED LOGIC TECHNOLOGY (ALT)

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Papers are solicited in the areas of CMOS platform technologies and applications (e.g., HPC, LOP, mobile, automotive, low temperature CMOS, etc.), logic devices and circuits, process integration schemes for advanced nodes, innovations in material, process and metrology techniques, and design technology co-optimization (DTCO) and system technology co-optimization (STCO). Platform technologies include state-of-the-art Si and beyond-Si channel devices, gate-all-around devices, stacked devices with diHerent polarity transistors, advanced interconnect, novel power distribution integration schemes, heterogenous 2.5D/3D integration schemes, and BEOL compatible transistors. Device architecture, device design and analysis, process integration, module advancements in process and patterning, metrology, physical layout eHects, techniques for reduced variability, yield, thermal management, methodologies, and solutions for DTCO/STCO in the solicited areas are of high interest.

EMERGING DEVICE and COMPUTE TECHNOLOGY (EDT)

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Papers are solicited on emerging nano-electronic devices and physics. This includes devices based on novel transport and control mechanisms such as tunnel FET, negative capacitance FET, cold-source FET, cryogenic devices, topological materials and devices, phase transitions, ferroelectrics and quantum eHects. Devices based on low-dimensional systems including 2D materials, CNTs, nanowires, single electron transistors and quantum dots are welcomed. Exploratory devices with novel device functions and/or novel materials for neuromorphic compute, approximate and analog compute, and non-charge-based compute such as spintronics are key topics. Furthermore, emerging state machines and time dynamical compute systems are also of interest. Qubit devices as well as devices and systems designed to enable quantum computing, quantum simulation and quantum annealing are of high interest. Papers in EDT focus primarily on device physics and novel elaboration concepts.

MEMORY TECHNOLOGY (MT)

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Papers are solicited across various domains in memory and storage technologies. This encompasses advancements and scaling in established technologies like SRAM, DRAM, and Flash, as well as breakthroughs in emerging innovations such as MRAM, PCM, FRAM, RRAM, ECM, Cross-Point memory, organic memory, and NEMS-based memory. These include research pertaining to materials and devices for memory and selector in electrostatic and atomistic switching mechanisms, as well as the design and implementation of memory cells and arrays in 3D constructs, including stacking and tiering, alongside read/write access mechanisms. Additionally, submissions of novel approaches to homogenous or heterogenous integration and manufacturing techniques of memory in semiconductor fabrication or packaging assembly are welcome. Authors are also invited to present papers focusing on reliability characterization and physics exploration, as well as improvements through manufacturing and usage algorithm, such as wear leveling. Furthermore, contributions addressing the span-expanding and gap-bridging of tiering and hierarchy in memory subsystem are encouraged, as are those addressing memory subsystems tailored to a broad spectrum of computing needs, ranging from mobile to large-scale platforms for client to cloud computing, encompassing both general-purpose and AI-based architectures. Papers disclosing novel physics and computing architecture may be transferred to other technical sections such as EDT or NC at the discretion of the committee.

MODELING and SIMULATION (MS)

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Papers are solicited on theoretical approaches to electronic devices, including logic, memory, optical components, interconnects, and (bio)sensors. Theoretical approaches include analytical, numerical, statistical, and machine-learning/AI-based methods applied to structures ranging from atomistic to device dimensions, and up to full-chip dimensions, including physics-based compact modeling. Central to submissions is the innovation of devices, whether through predictive insight into novel device concepts, predictive analysis demonstrating significant device improvements, breakthroughs in theoretical understanding of device operation, advancements in knowledge of device processing facilitating enhanced device performance, novel insights into variability, reliability, and yield issues, or breakthroughs in device optimization based on DTCO. Topics also include ab-initio/atomistic materials modeling, neuromorphic computing modeling, quantum computing, spintronics, low-dimensional devices, ferroelectrics, thermal modeling, 3D/heterogeneous integration, and electrochemical/ mechanical devices. Encouragement is given for comparison with experimental data, model calibration, and utilization of multi-scale simulation chains.

NEUROMORPHIC and NOVEL COMPUTING (NC):

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Papers are solicited in areas related to memory and logic devices, circuits, and algorithms for new and unconventional compute paradigms, including but not limited to neuromorphic computing and other artificial intelligence (AI) acceleration techniques. This includes, for example, analog/mixed-signal computing, in-memory computing devices and circuits for deep learning, probabilistic computing, bio-inspired computing such as spiking neural networks, reservoir computing, combinatorial optimization, content-addressable memory, etc. Use cases in the datacenter as well as on the edge, e.g. in-sensor computing, are contemplated. Demonstration of novel device concepts improving computational eHiciency, full hardware integration, device-algorithm co-optimization to mitigate non-ideal device properties, and real-world applications are of high interest. Papers on near-memory computing may be transferred to MT, and papers centered on optical or quantum computing may be transferred to EDT, at the discretion of the committee.