Paper 2.1, Stacked Nanosheet Channel with C-type Metal Contact

• Paper 2.1 with caption 

Individual images:

• Paper 2.1 Figure 13a & b   

• Paper 2.1 Figure 13a  

• Paper 2.1 Figure 13b 

Paper 3.4, A Materials-Device Co-Design Framework for Realizing Ultra Energy-Efficient All-2D-Spin-Logic Circuits with 2D-Materials

• Paper 3.4 with caption 

• Paper 3.4 Figure 12 

Paper 6.3, Highly Manufacturable, Cost-Effective, and Monolithically Stackable 4F2 Single-Gated IGZO Vertical Channel Transistor (VCT) for sub-10nm DRAM

• Paper 6.3 with caption 

• Paper 6.3 Figure 8  

Paper 8.1, Wafer-Level-Integrated Vertical-Waveguide sub-Diffraction-Limited Color Splitters

• Paper 8.1 with caption

• Paper 8.1 Figure 1 

• Paper 8.1 Figure 6

• Paper 8.1 Figure 7

Paper 9.7, DrGaN: an Integrated CMOS Driver-GaN Power Switch Technology on 300mm GaN-on-Si with E-mode GaN MOSHEMT and 3D Monolithic Si PMOS

• Paper 9.7 with caption

• Paper 9.7 Figure 2

• Paper 9.7 Figure 3b

• Paper 9.7 Figure 11

Paper 10.1, Status and Performance of Integration Modules Toward Scaled CMOS with Transition Metal Dichalcogenide Channel

• Paper 10.1 with caption

• Paper 10.1 Figure 6

• Paper 10.1 Figure 11 

Paper 12.1, Hardware Demonstration of Feedforward Stochastic Neural Networks with Fast MTJ-based p-bits

• Paper 12.1 with caption

• Paper 12.1 Figure 1c

• Paper 12.1 Figure 2a

Paper 15.7, NVDRAM: A 32Gb Dual Layer 3D Stacked Non-Volatile Ferroelectric Memory with Near-DRAM Performance for Demanding AI Workloads

• Paper 15.7 with caption

• Paper 15.7 Figure 5

Paper 21.5, Low Voltage (<1.8V) and High Endurance (>1M) 1-Selector/1-STT-MRAM with Ultra-Low (1 ppb) Read Disturb for High Density Embedded Memory Arrays

• Paper 21.5 with caption

• Paper 21.5 Figure 1a

• Paper 21.5 Figure 1b

• Paper 21.5 Figure 5

Paper 23.2, 3D Stackable CNTFET/RRAM 1T1R Array with CNT CMOS Peripheral Circuits as BEOL Buffer Macro for Monolithic 3D Integration with Analog RRAM-based Computing-In-Memory

• Paper 23.2 with caption

• Paper 23.2 Figure 1b

• Paper 23.2 Figure 1d 

Paper 24.1, Experimental Demonstration and Modeling of a Ferroelectric Gate Stack with a Tunnel Dielectric Insert for NAND Applications

• Paper 24.1 with caption 

• Paper 24.1 Figure 1  

• Paper 24.1 Figure 2b 

• Paper 24.1 Figure 11   

Paper 25.6, Dual-Wavelength Neural Probe for Simultaneous Opto-Stimulation and Recording, Fabricated in a Monolithically Integrated CMOS/Photonics Technology Platform

• Paper 25.6 with caption 

• Paper 25.6 Figure 2 

• Paper 25.6 Figure 2c 

• Paper 25.6 Figure 6d

Paper 29.2, Demonstration of a Stacked CMOS Inverter at 60nm Gate Pitch with Power Via and Direct Backside Device Contacts

• Paper 29.2 with caption 

• Paper 29.2 Figure 4

• Paper 29.2 Figure 15

• Paper 29.2 Figure 16

Paper 29.6, Complementary Field-Effect Transistor (CFET) Demonstration at 48nm Gate Pitch for Future Logic Technology Scaling

• Paper 29.6 with caption

• Paper 29.6 Figure 1

• Paper 29.6 Figure 5

Paper 33.2, 3D Monolithically Integrated Device of Si CMOS Logic, IGZO DRAM-like, and 2D MoS2 Phototransistor for Smart Image Sensing

• Paper 32.2 with caption

• Paper 32.2 Figure 1a

• Paper 32.2 Figure 2b

Paper 34.6, THz InP/GaAsSb DHBTs with Record 𝑓AVG=800 GHz: Characterization to 330 GHz

• Paper 34.6 with caption

• Paper 34.6 Figure 3

• Paper 34.6 Figure 5

• Paper 34.6 Figure 14

Paper 40.1, A 0.5μm Pixel 3-layer Stacked CMOS Image Sensor with Deep Contact and In-Pixel Cu-Cu Bonding Technology

• Paper 40.1 with caption

• Paper 40.1 Figure 1c

• Paper 40.1 Figure 2

Paper 41.1, Fluorine Anion-Doped Ultra-Thin InGaO Transistors Overcoming Mobility-Stability Trade-Off

• Paper 41.1 with caption

• Paper 41.1 Figure 1

• Paper 41.1 Figure 2

• Paper 41.1 Figure 15