2017 IEDM Tutorials
The tutorials are in their seventh year and are 90 minute stand alone presentations on specialized topics taught by world-class experts. These tutorials will provide a brief introduction to their respective fields, and facilitate understanding of the technical sessions. In contrast, the traditional short courses are intensive full-day events focused on a single technical topic.
The tutorial sessions will take place on Saturday, December 2nd. Three tutorials are given in parallel in two time slots, at 3:15 p.m. and 5:00 p.m. respectively.
Topics presented at 3:15 – 4:45 p.m:
- The Evolution of Logic Transistors toward Low Power and High Performance IoT Applications, Dae Won Ha, Samsung Electronics – For more than 4 decades, logic transistors have been successfully evolved to satisfy the ever-increasing demands for high performance and low power consumption. Three innovative technologies have been applied to suppress the abrupt increase in standby and/or dynamic power consumption; HKMG (Hi-K Metal Gate) and mobility enhancement S/D strain engineering and FinFET device architecture. This tutorial will cover the evolution of logic transistors from past to future, starting with the limitation of planar transistors, i.e., excess standby power consumption. Then, today’s state-of-the-art FinFET technologies will be introduced in detail, including layout, key design rules, short channel effects, multi-Vth engineering, local layout effects (LLE), variability, and so on. Finally, potential future GAA (Gate-All-Around) device architectures such as MBCFET (Multi-Bridge Channel FET) and VFET (Vertical FET) will be discussed. It will give attendees an overview and background sufficient to allow them to follow and participate in discussion on logic transistor technologies, especially focusing on FinFET.
- Hardware Opportunities in Cognitive Computing: Near- and Far-term, Geoffrey Burr, IBM Research-Almaden – For more than 50 years, the capabilities of Von Neumann-style information processing systems — in which a “memory” delivers operations and then operands to a dedicated “central processing unit” — have improved dramatically. While it may seem that this remarkable history was driven by ever-increasing density (Moore’s Law), the actual driver was Dennard’s Law: the amazing realization that each generation of scaled-down transistors could actually perform better, in every way, than the previous generation. Unfortunately, Dennard’s Law terminated some years ago, and as a result, Moore’s Law is now slowing considerably. In a search for ways to continue to improve computing systems, the attention of the IT industry has turned to approaches for computing that are not so dependent on getting billions of devices to work absolutely perfectly. One such approach is to move towards Non-Von Neumann algorithms, and in particular, to Cognitive Computing architectures motivated by the human brain. In this talk, I will review recent progress towards hardware implementation and/or acceleration of such brain-inspired computing architectures. This progress ranges from systems that combine conventional CMOS devices in different and unconventional ways, to systems built around emerging NVM (Non-Volatile Memory) devices; and from systems designed to accelerate conventional ML (Machine Learning) through hardware innovation, to systems that seek to transcend the limitations of current ML algorithms (such as the requirement for batch-based learning using vast datasets of static and labeled data).
- Silicon Photonics for Next-Generation Optical Interconnects, Joris Van Campenhout, IMEC – Demand for data communication in cloud datacenters is projected to grow exponentially in the next few years. Leveraging the advanced manufacturing capability available in CMOS Fabs, silicon photonics has emerged in the past decade as a highly prospective integrated photonics technology, enabling scalable, Tb/s scale optical interconnects. In this tutorial, we will take a deep dive into the capabilities of this platform. First, we will discuss the short-reach optical interconnect scaling trends and industry roadmap. Next, we will discuss a variety of silicon photonics devices, covering passive devices as well as high-speed Si or GeSi modulators and photodetectors capable of operating at data rates as high as 100Gb/s. We will describe how these building blocks can be combined with low-power CMOS driving circuits to implement Tb/s scale electro-optical transceivers with unsurpassed bandwidth density and power efficiencies below 5pJ/bit. Finally, we will discuss future prospects for integrating GaAs and InP based laser sources on silicon by direct epitaxial growth.
Topics presented at 5:00 p.m.-6:30 p.m:
- Negative Capacitance Transistors, Sayeef Salahuddin, University of California, Berkeley – The physics of ordered and correlated systems allow for fundamental improvement of the energy efficiency when a transition happens between two distinguishable states. For ferroelectric materials where such order forms due to interaction between many dipoles, thermodynamics dictate that charge can be switched with much lower energy compared to conventional dielectrics. This leads to a situation where a ferroelectric material can be stabilized at a state of negative capacitance. In this tutorial, I shall discuss the physical origin of negative capacitance and how it can be stabilized to obtain an amplification of the electrostatic field. When combined with the gate of ta transistor, this state of stabilized negative capacitance could lead to reduction in the supply voltage and/or increase of the ON current of a transistor. I shall discuss our understanding of this phenomena based on the most recent experimental results and possible pathways to optimize transistor performance for scaled nodes.
- Fundamental, Thermal, and Energy Limits of PCM and ReRAM, Eric Pop, Stanford University – This tutorial will introduce the operation mechanism and fundamental limitations of non-volatile phase-change memory (PCM) and resistive random access memory (ReRAM). The two memory types will be presented in context, with emphasis placed on their thermal and energy limitations, down to atomic scale dimensions. We will also discuss modern devices, challenges, test structures, and simple models required to understand their operation. The tutorial will give attendees an overview and background sufficient to allow them to think and actively contribute to the discussion on the ultimate (i.e. sub-5 nm) limits of these memory technologies.
- 2.5D Interposers and High Density Fanout Packaging as Enablers for Future Systems Integration, Venkatesh Sundaram, Georgia Institute of Technology – As Moore’s law struggles to sustain the performance gains and cost reduction that has fueled the growth in electronics systems, advanced packaging has stepped in to complement transistor scaling with system scaling at the package level. Two major packaging technologies, 2.5D interposers and high density fan-out (HDFO), have gained prominence in recent years in enabling multi-die integration for higher bandwidth, lower power consumption and reduced design cycle times. This tutorial will provide an introduction to interposer and fanout packaging technologies, market drivers, application examples and infrastructure evolution, as well as latest state of the art innovations. In addition to silicon, organic and glass 2.5D interposers, emerging fanout technologies such as InFO used in Apple iPhones and embedded bridge (EMIB) introduced by Intel will also be explained. Interposers bridge the interconnect gap between back end of the line (BEOL) pitch and current organic BGA packages. Interposers started out as a 2.5D multi-die integration step towards full 3D IC stacking. However, they are now viewed as a system integration platform with pervasive applications now and into the future. In the past couple of years, the technology development and manufacturing infrastructure maturity has been progressing rapidly. The first volume products using silicon interposers have been introduced in the graphics market since 2015 integrating high bandwidth memory (HBM) and GPUs. Several other applications are also exploring product designs based on interposer concepts. It is certainly an exciting time for interposer technologies. Emerging alternatives such as glass and new organic interposers are promising cost reduction from wafer based silicon interposers that should enable a much broader adoption of interposers. Although fanout packaging emerged in the first years of this century with approaches such as eWLB by Infineon, the introduction of high density fanout packages by TSMC to package application processors in iPhones in 2016-2017 has generated unprecedented excitement about the promise of this system integration approach that eliminates traditional substrate and assembly processes. This year’s tutorial by one of the top advanced packaging experts in the world includes significant new material covering the latest advances in 2.5D and 3D interposers, and high density fanout packages. The course will address both fundamentals of interposer and fanout technology, as well as applications and supply chain infrastructure. The course will be interactive and include audience Q&A and samples of latest interposer demonstrators will be passed around for a hands-on experience.
TO PERMIT SPONTANEOUS AND CANDID DISCUSSION, NO VERBATIM RECORDING BY TAPE OR CAMERA WILL BE PERMITTED IN ANY OF THE TUTORIALS.