2020 IEDM Tutorials

The tutorials are in their eleventh year and are stand alone presentations on specialized topics taught by world-class experts. These tutorials will provide a brief introduction to their respective fields, and facilitate understanding of the technical sessions. In contrast, the traditional short courses are focused on a single technical topic.

All Tutorials will be On Demand starting on Saturday, December 5 (will be held PST)

Live Q&A with the Lecturers for Tutorials 1-3 will be on Saturday, December 12, 8:00AM-8:45AM (PST)

Live Q&A with the Lecturers for Tutorials 4-6 will be on Saturday, December 12, 8:45 AM- 9:30 AM (PST)

Tutorial 1: Quantum computing technologies

Speaker: Maud Vinet (Leti)


Thanks to superposition and entanglement, quantum computing is expected to extend the high performance computing roadmap at the condition of being able to operate a large number of qubits. First quantum reported quantum processors mostly rely on superconducting qubits. In comparison to other existing platforms such as photonic waveguides1, trapped ions2, and spin qubits3, the success of superconducting qubits can be attributed both to the fact that this technology is accessible by academic cleanrooms and that it benefits from advances in high-performance microwave instrumentation developed for telecommunication industry. On the other hand, Si-based QC appears as a promising approach to build a quantum processor; thanks to the size of the qubits, the quality of the quantum gates and the VLSI ability to fabricate billions of closely identical objects. And finally recently trapped ions and photonic based quantum processors have also attracted a lot of interest by being taken in charge by engineering teams with technologies that could be scaled up.

In this tutorial, we will start by a reminder on quantum computing principles and then we will identify the qubits figures of merit required to build a quantum processor. We will benchmark the experimental platforms and provide a system perspective on the challenges to reach high number of qubits, let’s say above 10,000.

Speaker’s Bio:

Maud Vinet (CEA-Leti, University Grenoble Alpes, France) is currently leading the quantum computing program in Leti. She is a researcher and together with Tristan Meunier (CNRS) and Silvano de Franceschi (Fundamental research division from CEA), they received an ERC Synergy grant in 2018 to develop silicon based quantum computer.

She defended a PhD of Physics from University of Grenoble Alps and was hired Leti in 2001 as a CMOS integration and device engineer. From 2009 to 2013, she spent 4 years with IBM to develop Fully Depleted SOI with IBM and STMicroelectronics. In 2015, she spent 6 month with Globalfoundries in Malta, NY to launch 22FDX program.

From 2013 to 2018, she managed the Advanced CMOS integration team activities in Leti (~50 people). In 2019, she was appointed project leader for the quantum computing program in Leti.

Maud Vinet authored or co-authored about 200 papers, she owns more than 70 patents related to nanotechnology and her Google h-index is 42.

Tutorial 2: Advanced Packaging Technologies for Heterogeneous Integration

Speaker: Ravi Mahajan and Sairam Agraharam (Intel)


Advanced packaging technologies are critical enablers of Heterogeneous Integration (HI) because of their importance as compact, power efficient platforms.  This tutorial will start by describing the role of advanced packaging in the overall HI landscape using the HI roadmap as a reference.  The tutorial will then describe the key physical and performance attributes of advanced packaging architectures and describe their evolution. Different packaging architectures will be compared primarily on the basis of their physical interconnect capabilities.  Key features in leading edge 2D and 3D technologies, such as EMIB, Silicon Interposer, Foveros and Co-EMIB will be described and a roadmap for their evolution will be presented.  This will be followed by a high-level discussion of Assembly and Test flows.  Challenges and opportunities in developing advanced package architectures will be discussed.  The scope of the discussion will include design for performance (i.e. ensuring efficient power delivery, high-speed signaling and thermal management), thermo-mechanical robustness, manufacturing considerations, materials and reliability. Reference will also be made to key enabling fields such as modeling, metrologies and equipment.  The tutorial will conclude with a discussion of overall opportunities and challenges in driving the advanced package roadmap forward.

Speaker’s Bio:

Ravi Mahajan is an Intel Fellow responsible for Assembly and Packaging Technology Pathfinding for future silicon nodes. Ravi joined Intel in 1992 after earning Ph.D. in Mechanical Engineering from Lehigh University.  He holds the original patents for silicon bridges that became the foundation for Intel’s EMIB technology. His early insights have also led to high-performance, cost-effective cooling solutions for high-end microprocessors and the proliferation of photo-mechanics techniques used for thermo-mechanical stress model validation. His contributions during his Intel career have earned him numerous industry honors, including the SRC’s 2015 Mahboob Khan Outstanding Industry Liaison Award, the 2016 THERMI Award from SEMITHERM, the 2016 Allan Kraus Thermal Management Medal & the 2018 InterPACK Achievement award from ASME, the 2019 “Outstanding Service and Leadership to the IEEE” Awards from IEEE Phoenix Section & Region 6 and most recently the 2020 Richard Chu ITherm Award For Excellence. He is one of the founding editors for the Intel Assembly and Test Technology Journal (IATTJ) and currently VP of Publications & Managing Editor-in-Chief of the IEEE Transactions of the CPMT.  He has been long associated with ASME’s InterPACK conference and was Conference Co-Chair of the 2017 Conference.  Ravi is a Fellow of two leading societies, ASME and IEEE.  He was named Intel Fellow in 2017.

Sairam Agraharam is a Senior Principal Engineer responsible for developing and enabling successful die package integration with high yield/reliability, new first level interconnect schemes/pitch scaling, and novel heterogeneous package architectures/process flows for Intel products.  Through his nearly two decade long career, Sai has been instrumental in the successful resolution of many chip-package design, materials, process and reliability interactions with Cu bump based first level interconnect and low-K dielectrics, resulting in successful deployment of scaled packaging technologies.  He led the teams that enabled Intel’s first lead-free / halogen free packages and successfully integrated Intel’s first thick metal passivation architecture.   He played a pivotal role in the development and successful implementation of novel heterogeneous package architectures such as EMIB and Foveros in Intel products and continues to take leadership roles as a technologist for future scaling.  Sairam joined Intel in 2000 after receiving his Ph.D in Chemical engineering from Georgia Institute of technology.  He has 20 patents spanning the areas of die-package ILD stress reduction, novel packages and package interconnect architectures.

Tutorial 3: Memory-Centric Computing Systems

Speaker: Onur Mutlu (ETH)


Computing is bottlenecked by data. Large amounts of application data overwhelm storage capability, communication capability, and computation capability of the modern machines we design today. As a result, many key applications’ performance, efficiency and scalability are bottlenecked by data movement. We describe three major shortcomings of modern architectures in terms of 1) dealing with data, 2) taking advantage of the vast amounts of data, and 3) exploiting different semantic properties of application data. We argue that an intelligent architecture should be designed to handle data well. We show that handling data well requires designing architectures based on three key principles: 1) data-centric, 2) data-driven, 3) data-aware. We give several examples for how to exploit each of these principles to design a much more efficient and high performance computing system. We will especially discuss recent research that aims to fundamentally reduce memory latency and energy, and practically enable computation close to data, with at least two promising novel directions: 1) performing massively-parallel bulk operations in memory by exploiting the analog operational properties of memory, with low-cost changes, 2) exploiting the logic layer in 3D-stacked memory technology in various ways to accelerate important data-intensive applications. We discuss how to enable adoption of such fundamentally more intelligent architectures, which we believe are key to efficiency, performance, and sustainability. We conclude with some guiding principles for future computing architecture and system designs.

Speaker’s Bio:

Onur Mutlu is a Professor of Computer Science at ETH Zurich. He is also a faculty member at Carnegie Mellon University, where he previously held the Strecker Early Career Professorship.  His current broader research interests are in computer architecture, systems, hardware security, and bioinformatics. A variety of techniques he, along with his group and collaborators, has  invented over the years have influenced industry and have been employed in commercial microprocessors and memory/storage systems. He obtained his PhD and MS in ECE from the University of Texas at Austin and BS degrees in Computer Engineering and Psychology from the University of Michigan, Ann Arbor. He started the Computer Architecture Group at Microsoft Research (2006-2009), and held various product and research positions at Intel Corporation, Advanced Micro Devices, VMware, and Google.  He received the IEEE Computer Society Edward J. McCluskey Technical Achievement Award, ACM SIGARCH Maurice Wilkes Award, the inaugural IEEE Computer Society Young Computer Architect Award, the inaugural Intel Early Career Faculty Award, US National Science Foundation CAREER Award, Carnegie Mellon University Ladd Research Award, faculty partnership awards from various companies, and a healthy number of best paper or “Top Pick” paper recognitions at various computer systems, architecture, and hardware security venues. He is an ACM Fellow “for contributions to computer architecture research, especially in memory systems”, IEEE Fellow for “contributions to computer architecture research and practice”, and an elected member of the Academy of Europe (Academia Europaea). His computer architecture and digital logic design course lectures and materials are freely available on YouTube, and his research group makes a wide variety of software and hardware artifacts freely available online. For more information, please see his webpage at

Tutorial 4: Imaging Devices and Systems for Future Society

Speaker: Yusuke Oike (Sony Semiconductor Solutions)


The evolution of image sensors and the prospects utilizing advanced imaging technologies promise to improve our quality of life. Since CMOS image sensors have surpassed CCDs with the advent of column-parallel ADCs and back-illuminated technology, the image sensor application is expanding to mobile devices, wearables, medical solutions, security networks, factory automation and autonomous driving. Stacking technologies are now drastically accelerating the performance improvement and enhancing the functionality of imaging devices. The fine pitch connection between the pixel and logic layers makes the pixel parallel circuit architecture available for the next evolution. New materials for photoconductive layer extend the sensitivity to a wide range of wavelengths. This tutorial introduces a broad overview of the key device technologies for image sensors, as well as circuit techniques, image signal processing and performance characteristics, that enable imaging applications in various fields. The next challenge of imaging system will be discussed for future society, where the imaging devices integrate edge computing functions and expand the sensing capability of spatial depth, temporal dynamics and invisible light.

Speaker’s Bio:

Yusuke Oike is a Distinguished Engineer of Sony Corporation and a Deputy Senior General Manager of Sony Semiconductor Solutions Corporation. He joined Sony Corporation, where he was involved in research and development of architectures, circuits and devices for image sensors, after he received Ph.D. degree in electronic engineering from the University of Tokyo in 2005. From 2010 to 2011, he was a Visiting Scholar at Stanford University, CA, USA. Currently he is responsible for developing CMOS image sensors at Sony Semiconductor Solutions. His research interests include pixel architecture, mixed-signal circuit design for image sensors and image processing algorithms. He is also a Director of Sony Advanced Visual Sensing AG in Zurich. He was a member of Technical Program Committee of ISSCC and VLSI Symposium, and he currently serves as the Program Chair of VLSI Symposium on Circuits 2021.

Tutorial 5: Innovative technology elements to enable CMOS scaling in 3nm and beyond – device architectures, parasitics and materials

Speaker: Myung-Hee Na (imec)


CMOS technology is crucial for the foundation of next-generation computing in various application domains. This fact fuels a strong technical appetite for further CMOS scaling down to 3nm and beyond.   However, this necessitates the development of new device architecture beyond FinFET in order to overcome the barrier of CMOS scaling as it exists now.

In this study, we will review a few key innovative device architectures such as Forksheet and CFET for next-generation CMOS device architectures.  We will share the results from device to block level performance to provide comprehensive views of new architectures.  However, it should be pointed out that innovative device architectures alone may not be sufficient to enable cell and block-level scaling. Since performance impact and routability of a block strongly depends on interconnects in advanced architectures, we believe the innovative interconnects should be simultaneously considered in combination with device architectures in sub-5nm node. As an example, we will provide a deep dive into smart power delivery with buried power rails and the optimization of power distribution networks .

Finally, we plan to discuss the challenges and opportunities of 2D materials for beyond SI channel for next-generation CMOS scaling.

Speaker’s Bio:

Dr. Myung-Hee Na is a semiconductor technologist and currently work at imec as the Vice President of Technology Solutions and Enablement. She is currently responsible for CMOS and AI hardware technology research for new semiconductor era. Myung-Hee received a Ph.D in Physics and started her career at IBM in 2001 where she held various technical, managerial and executive roles until early 2019.  At IBM, she successfully led Research and Development for multiple generations of semiconductor technologies, including high-K metal gate, FinFET, and Nanosheet development.  Moreover, she has co-authored numerous research papers and holds several U.S. and international patents.

Tutorial 6: STT and SOT MRAM technologies and its applications from IoT to AI System

Speaker: Tetsuo Endoh (Tohoku University)


I will overview STT MRAM technology for e-Memory application such as SRAM and e-Flash. Next, for higher speed application, I will show SOT MRAM technology. Finally, I will discuss IoT MCU and AI Processor with CMOS/MTJ hybrid technology. (this abstract is to be updated)

Speaker’s Bio:

Tetsuo Endoh joined ULSI Research Center Toshiba Co. in 1987 and was engaged in the R&D and Mass-production of NAND Memory. He became a lecturer at the Research Institute of Electrical Communication, Tohoku University in 1995. Now, He is a professor at the Graduate School of Engineering, Director of the Center for Innovative Integrated Electronic Systems (CIES) and Deputy director of the Center for Science and Innovation in Spintronics (CSIS) of Tohoku University. His current interests are advanced memory technology, 3D structure device, beyond-CMOS technology and low power processor technology such as 3D NAND memory, STT-/SOT-MRAM, Vertical GAA MOSFET, CMOS/Spintronics Hybrid circuit, Spintronics-based Non-Volatile Logic from IoT processor to AI processor, and so on. He is also interested in power-management technology, such as GaN on Si based power devices and power electronics from circuits to module/system for automotive applications and so on.

He received the 14th Prime Minister’s Award for its Contribution to Industry-Academia-Government Collaboration in 2016. He received National Invention Award “the 21st century Encouragement of Invention Prize” for contribution to invention of 3D NAND memory in 2017.