The tutorials are in their ninth year and are 90 minute stand alone presentations on specialized topics taught by world-class experts. These tutorials will provide a brief introduction to their respective fields, and facilitate understanding of the technical sessions. In contrast, the traditional short courses are intensive full-day events focused on a single technical topic.
The tutorial sessions will take place on Saturday, December 7th. Three tutorials are given in parallel in two time slots, at 2:45 p.m.and 4:30 p.m. respectively.
Tutorials 2:45 pm – 4:15 p.m.
- Oxide Semiconductors and Application, Hideo Hosono, Tokyo Institute of Technology
DOWNLOAD ABSTRACT – Oxide semiconductor has a long research history comparable to Si/Ge semiconductors but almost no distinct device application was seen up to ~2012. Since then, oxide TFTs represented by amorphous IGZO-TFTs are practically used to drive pixels of advanced displays such as high precision LCDs and large-sized OLED-TVs. Oxide semiconductors rather differ from conventional semiconductors such as Si in several respects. This striking difference arises from that in chemical bonding nature, i.e., ionic vs. covalent. Understanding oxide semiconductors in comparison with Si will enable us to get a comprehensive view for semiconducting materials. In this lecture I talk about historical background, chemical bonding, p/n-orientation and band lineup, materials design concept and concrete materials for crystalline and amorphous oxide semiconductors, and application to TFTs as channel semiconductors and perovskite LEDs as electron injection/transport layer. Emphasis is placed on crystalline and amorphous IGZO-TFTs and their characteristics and instability issue. Recent reviews and monographs are also introduced for further reading.
- In-memory Computing for AI, Abu Sebastian, IBM Research – Zurich
DOWNLOAD ABSTRACT – The explosive growth in data-centric artificial intelligence related applications necessitates a radical departure from traditional von Neumann computing systems, which involve separate processing and memory units. In-memory computing is one such approach where certain computational tasks are performed in place in the memory itself. This is achieved by exploiting in tandem the physical attributes of the memory devices, its array-level organization and peripheral circuitry as well as the control logic. Any computational task that is realized within the confines of these three units could be called in-memory computing. However, the key distinction is that at no point during computation, the memory content is read back and processed at the granularity of a single memory element. Both charge-based as well as resistance-based memory devices are being explored for in-memory computing. In-memory computing can be applied both to reduce the computational complexity of a problem via analog computing as well as to reduce the amount of data being accessed by performing computations inside the memory arrays. In this tutorial, I will provide a broad overview of the key computational primitives enabled by these memory devices as well as their applications spanning scientific computing, signal processing, machine learning, deep learning and stochastic computing. I will conclude with a discussion on the challenges and new directions of research.
- Magnetic Field Sensors, Keith Green, Texas Instruments
DOWNLOAD ABSTRACT – The objective of this tutorial is to introduce magnetic field sensing to an audience that is not familiar with it. Applications and several magnetic field sensing technologies will be discussed. The majority of the tutorial will be spent on Hall-effect sensing, which is the most widely used technology. In particular, the tutorial will focus on integrated, silicon-based Hall sensors. Key performance characteristics of the sensing element will be explained. Also, attendees will have access to hand-on demonstrations to help them better understand Hall-effect sensors.
Tutorials 4:30 pm – 6:00 pm
- Cryogenic MOSFET Modeling, Christian Enz, EPFL
DOWNLOAD ABSTRACT – There is currently a large effort to try to miniaturize quantum computers taking advantage of solid-state technologies enabling a potentially large number of qubits operating in regimes that allow superposition and entanglement. CMOS is the preferred technology for building the qubit array and mixing it with the control and readout electronics taking advantage of the cryogenic temperature to operate the electronics at lower power and/or faster. The design and optimization of these CMOS analog and digital circuits need a compact transistor model that is valid down to cryogenic temperatures. Unfortunately, the current MOSFET compact models do not scale properly with temperature down to such low temperature. This tutorial will address this limitation. It starts with an assessment of the analog performance at cryogenic temperatures using the simplified EKV MOSFET model. The main effects occurring at cryogenic temperature are then described and a physics-based MOSFET model that scales down to ultra-low temperatures is then presented.
- Ferroelectric Memories and Beyond, Johannes Műller, Globalfoundries
DOWNLOAD ABSTRACT – Recent advances in scaling and CMOS-compatible implementation of ferroelectric thin films has sparked renewed interest to utilize the unique properties of these materials in advanced CMOS technology nodes. Led by the ferroelectric memory development and further fueled by new applications fields such as steep slope devices and neuromorphic applications, this field has seen a strong growth in R&D activity over the last decade. This tutorial will give an introduction to ferroelectric materials and devices with special emphasis on the utilization of hafnium oxide based thin films. The working principle as well as the challenges of capacitors based ferroelectric random access memory (FRAM), ferroelectric field effect transistor (FeFET) and ferroelectric tunnel junction (FTJ) will be reviewed. In addition, a brief outlook on beyond memory applications of CMOS-compatible ferroelectric thin films will be given.
- Sequential Integration, Perrine Batude, LETI
DOWNLOAD ABSTRACT – 3D sequential integration allows vertically stacking several layers of devices with a unique connecting via density above 108 via/mm2. However, the thermal stability of the lower tier(s) constrains the thermal budget of the sequentially processed upper tier(s).The first aim of this tutorial will be to present the main prospective application sectors, namely (i)Pursuing Moore’s law without resorting to MOSFETs scaling ii) Enabling alternative computing paradigms through close proximity between logic and memory units iii) offering new heterogeneous co‐integrations schemes for smart sensor arrays iv) adding low cost functionalities above ICs.
Moreover, major 3D sequential integration demonstrations examples will be reviewed revealing the rich diversity of stacked low temperature devices currently under study ranging from traditional low temperature Si MOSFETs, poly‐Si TFTs, junction‐less devices, carbon nanotubes, oxide semiconductors, etc.
This tutorial will give a synoptic view of all the key enabling process steps required to build high performance Si CMOS with thermal budget preserving the integrity of active devices and interconnects (top channel formation, gate stack reliability, junction’s activation, low resistivity gate realization, selective epitaxy, spacer’s formation) and will sketch a status on current low temperature device performance with respect to their high temperature counterparts.