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This talk will trace the evolution of the logic transistor over four decades of CMOS scaling, from the planar MOSFET era shaped by Dennard scaling, through strained silicon and high-k/metal gate innovations, to the FinFET transition that restored electrostatic control at deeply scaled dimensions, and onward to today’s gate-all-around nanosheet architecture. The presentation will examine the device-physics drivers behind each architectural shift, including short-channel control, parasitic resistance and capacitance, variability, power density, and manufacturability, and will discuss how these factors reshaped both transistor design and process integration. Building on that foundation, the tutorial will explore the next stages of scaling, including fork sheet concepts, vertically stacked complementary FETs (CFETs), backside power delivery, and the growing role of design-technology co-optimization. It will conclude with a forward-looking perspective on the opportunities and challenges of post-silicon channel option.

With CMOS technology scaling reaching some physical and economic limits the high-performance computing industry has introduced new technologies aiming to keep on offering improved performances to the product design community leveraging on new front-end process and assembly capabilities modifying the frontiers between the 2 words.
This trend intending to “de-integrate” is a real technological breakthrough after more than 60 years leveraging on CMOS integration driving to system on chip product architectures.

Showing some practical hardware developments highlighting spectacular process capabilities and product performances serving the field of chiplet product architecture.

On the other hand, derivative technologies such as CMOS image sensors and silicon photonics, 3D-stacking has entered high-volume manufacturing since several years with technology features that can be extended to other application domains. The rational of the move from 2D to 3D will be explained and technology principles and examples will be given mainly leveraging on STMicroelectronics own experience.

On top of process features, CAD capabilities have also to be developed and offered by EDA vendors enabling 2.5 and 3D product designs. Here again some developments with EDA vendors will be covered covering a set of tailored 3D capabilities.

Memory Wall has been a popular term lately in the AI Era, due to criticality of Data Storage and movement in Training and Inference workloads. Low latency, high Bandwidth, Low Power and Cost are all crucial to scale AI workloads to achieve the optimal Tokens/sec/$. SRAM and DRAM/HBM have been the main workhorses to provide the memory needs, but new solutions such as High Bandwidth Flash (HBF) are being introduced. This tutorial will go through the Memory subsystem, system level integration, scaling from past to present and how future memory technology candidates are being proposed to push the boundaries of Memory Wall in AI.

Large-scale AI systems have reinforced a memory roadmap centered on DRAM and HBM scaling for workloads dominated by capacity and bandwidth. However, adaptive computing applications impose additional constraints: persistent local states across idle phases, energy-efficient retraining, low-standby inference, probabilistic exploration and low-latency transfer between data with different lifetimes. In these regimes, neither non-volatility nor analog computing is needed everywhere, but both become valuable when matched to the right data and algorithmic roles.
This tutorial presents a device-level perspective on diverse memory technologies for adaptive in-memory computing. Rather than seeking a universal memory, we discuss how heterogeneous memories can cooperate, each operating where its physical properties are most useful. The focus is on the principles that make such cooperation meaningful: separating update and inference roles, exploiting device physics as computing primitives, reducing unnecessary data conversion, and turning memory-to-memory interfaces into mechanisms for transfer, adaptation, sampling or annealing.
The tutorial will position this approach with respect to DRAM/HBM-centric systems, review the opportunities and limits of analog in-memory computing, and discuss integration paths from 2.5D packaging to hybrid bonding and monolithic 3D. Selected experimental examples will illustrate how cooperative memories can support adaptive learning, probabilistic computing and optimization, while highlighting practical challenges in endurance, variability, precision, tiling, calibration and system-level mapping.

This tutorial presents a physics-grounded perspective on the application of artificial intelligence (AI) and machine learning (ML) across semiconductor modeling workflows, ranging from feature-scale process and device simulation to block-scale design technology co-optimization (DTCO). Anchored in governing PDEs and numerical methods, the tutorial highlights how ML augments, rather than replaces, physics-based solvers through surrogate modeling, operator learning, and solver acceleration. Applications of ML models to (a) device and process optimization, (b) compact model construction and extraction, and (c) stochastic variability are discussed with emphasis on physical consistency and robustness. The integration of these techniques into DTCO and design closure flows, for faster exploration of design-technology tradeoffs, is then examined. Finally, emerging agentic AI approaches for orchestrating end-to-end TCAD/EDA workflows are outlined.

We will discuss recent R&D advances in silicon-integrated modulators and photodetectors, targeting both upcoming 400G/lane “Fast-and-narrow” Pluggable Optics and Co-Packaged Optics. Next, we will cover active optical devices designed for future “Wide-and-Slow” approaches enabling high-density optical I/O with ultra-low power consumption, eventually targeting chip-to-chip interconnects. We will elaborate on advanced EIC-PIC assembly, packaging and co-design and outline our vision for ubiquitous, sub-pJ/bit wafer-level optical interconnects.