2017 IEDM Short Courses

Sunday, December 3, 2017

9:00 a.m. – 5:30 p.m.

IEDM will offer two, full-day short courses with in-depth coverage of logic and memory topics from world experts. Advance registration is recommended.

Short Course 1 – Boosting Performance, Ensuring Reliability, Managing Variation in sub-5nm CMOS

Course Organizer: Sandy Liao, Intel Corporation

In this short course six presenters from leading edge industry and government organizations will present their insights on the future of semiconductor technology and scaling beyond the 5nm node. The entire stack will be covered from device physics and transistor scaling, to interconnect to BEOL and extending to system level requirements. Each expert will first introduce the state-of the art technologies implemented for 7nm, and then proceed to discuss opportunities and challenges such as novel materials, integration schemes, architectures and design techniques which will aid us in bridging the gap to 5nm and beyond.

The first speaker in the course is Gen Tsutsui, who will discuss transistor performance boosters for the 5nm node and beyond. He will focus on Si and SiGe based FinFET technologies and discuss device performance optimization in terms of mobility and reliability, while discussing issues specific to the gate dielectric interface on SiGe channels. He will be followed by Steve Hung who will focus on gate stack engineering for advanced FinFETs, in particular from a Vt modulation perspective using work function engineered metal gate electrodes.

The interconnect challenges for sub-5nm nodes will be covered by Zsolt Tokei, in which he will cover both fabrication challenges related to EUV lithography, track height scaling in standard cells and novel conductor materials, as well as performance issues such as trade-offs in power rails and signal wires and circuit sensitivity to RC delay.

Two talks are dedicated to reliability issues at the transistor and BEOL level, respectively. First, Stephen M. Ramey will discuss transistor reliability issues such as gate oxide integrity, self-heating and transistor aging issues like BTI and hot carrier effects. He will be followed by Cathryn Christiansen who will cover BEOL reliability and performance challenges. She will start with an overview of reliability basics and improvements established for TDDB and EM through the 7nm node, and then follow-up with a discussion of potential boosters for 5nm nodes and beyond, including asymmetric spacing, thinner barriers/liners, alternative metals, lower-k dielectrics, airgap, and self-aligned vias. Putting everything into perspective, Andy Wei will wrap up the short course with a presentation about design-technology co-optimization for beyond the 5nm Node. The focus will be on an evaluation of device options beyond the 5nm node combined with a discussion of opportunities for system level innovation and future product requirements.


Short Course 2 – Memories for the Future: Devices, Technologies, and Architecture

Organizer: Kevin Zhang, Vice President, Design and Technology Platform, TSMC

Memories play an increasingly important role in all VLSI applications, ranging from high-performance computing, mobile and IoT to automotive, with each domain presenting their specific challenges. The demand for higher density, lower-power, and non-volatility has led to extensive investments across the industry into new memory technologies. Some of these so-called “emerging memories” are now reaching maturity, leading to new usage models based on their unique technology attributes. In this short-course, seven experts will cover a broad range of topics in the area of novel memory technology. First, Alfonso Maurelli will discuss the scaling of embedded nonvolatile memories for automotive applications. He will present the key technology scaling challenges and discuss their solutions to drive eNVM technology to meet the future requirements for automotive electronics. Nirmal Ramaswamy will follow with a technology overview of ReRAM technology for 3D Crosspoint Memories. This new class of memory boasts an unparalleled storage density while rivaling DRAM in terms of access latency. Thomas Mikolajick will discuss the key breakthroughs in Ferroelectric devices that have the potential to bring this memory into CMOS-based technologies for embedded applications, furthermore both ReRAM and ferroelectric devices are of interest for neuromorphic applications. Spin-Transfer-Torque (STT) MRAM has drawn lots of interest in recent years due to its unique memory characteristics and scalability. Danny Shum will present state-of-the-art STT-MRAM memories and their applications. To give a broader perspective on the future of memories  the short course will finish with two lectures on memory circuit design for low-power applications and future architectures  merging memory and logic to provide 1000X power efficiency improvements. They will be given by Jonathan Chang and Subhasish Mitra, respectively. Overall, the short-course is intended to provide both good breadth and in-depth coverage of the most recent memory technology advancements and the future direction.