Explore Expert Keynote

Artificial intelligence is no longer a distant idea or a science-fiction concept. It is here, and it is already transforming how we live, work, discover, and innovate. Large language models have expanded the realm of what is possible in ways that seemed unimaginable only a few years ago. Yet behind every AI breakthrough is a critical foundation: semiconductor technology. Semiconductors are enabling the AI revolution, and AI is now reshaping the future of semiconductors. It is driving the need for higher-performance, more energy-efficient compute while challenging the traditional limits of CPU scaling and system architecture. As AI moves from massive cloud-training environments to real-time inference at the edge, the requirements are becoming extraordinary: more memory, more bandwidth, lower latency, and far greater efficiency. Meeting this moment will require more than incremental improvement. We must innovate across the full stack—from materials and devices to architectures, packaging, and manufacturing—to deliver the performance per watt, memory bandwidth, and reliability the AI era demands.

This is why technology roadmaps are moving faster than ever before. Across the full stack, we are seeing a powerful new wave of innovation. Transistor architecture is evolving from FinFETs to gate-all-around structures, enabled by new channel materials, new interconnect metals, and new power-delivery schemes. Power delivery is also moving from the front side to the back side of the wafer, opening new design space and creating new opportunities for performance and efficiency. Looking ahead, Complementary Field Effect Transistor (CFET)  technology—combined with backside innovation—has the potential to reshape the industry again by enabling more compact layouts, higher computational throughput, and improved power efficiency. At the same time, heterogeneous integration is accelerating rapidly. EMIB, hybrid bonding, and chiplets are no longer future concepts; they are becoming essential building blocks for AI systems.

The reason is clear: AI is a data-movement challenge as much as it is a compute challenge. Domain-specific accelerators, increasingly specialized CPUs, and tightly coupled memory hierarchies are essential to remove bottlenecks and keep data flowing efficiently. Memory–compute integration—including high-bandwidth memory, near-memory processing, in-memory compute, and advanced 2.5D and 3D stacking—offers a powerful path to reduce energy-intensive data movement and sustain performance growth beyond the limits of monolithic scaling. Emerging technologies such as silicon photonics and optical interconnects can help overcome the limitations of electrical interconnects while significantly improving energy efficiency. And with Embedded Multi-Die Interconnect Bridge-TSV (EMIB-T), we can enable faster, more power-efficient, and more customizable connectivity between AI accelerators and high-bandwidth memory.

But as we transform the technology, we must also transform how we qualify it. Traditional device-centric qualification will not be sufficient for the systems we are building. The future requires system-level qualification that accounts for heterogeneous dies, advanced interconnects, thermal gradients, power-delivery integrity, data retention, and workload-dependent degradation. Quality must move earlier in the lifecycle, supported by stronger defect detection, richer traceability from materials to package, predictive reliability models, and tighter feedback loops across design, process control, test, and field operation. Just as importantly, we must embed sustainability and ethics into the foundation of our work. The AI-intensive future will carry environmental and social costs unless we act now. That means moving beyond carbon offsets toward intrinsic sustainability—designing systems that are efficient by nature—and advancing an equitable intelligence model supported by greater supply-chain transparency.

This is the opportunity before us. AI demand and semiconductor scaling are converging to redefine manufacturing as an integrated, reliability-led platform for the next generation of compute. The demands of AI hardware will continue to grow, and the choices we make today will determine how responsibly and sustainably that growth is realized. We have both the opportunity and the responsibility to shape this future with purpose, discipline, and bold innovation.

As AI workloads continue to scale, overall system performance is increasingly determined by the interplay between compute and memory performance. This drives demand for high bandwidth, power efficiency, and reliability. Limits in Cell scaling has accelerated the transition from 2D to 3D memory architectures and, as this shift progresses, the competitive performance of AI memory products is now increasingly driven by Peripheral (Peri) transistor technology.

Wafer bonding technology is fundamentally reshaping memory architecture by decoupling Cell and Peripheral wafer fabrication. This separation enables the integration of various performance boosters and allows for the independent optimization of Peripheral (Peri) technology. However, this shift alone does not guarantee successful innovation in the memory domain. Memory systems remain stringently constrained by cost reduction, the need for high-voltage operation, pitch-limited design rules, leakage control, and reliability requirements. Furthermore, the increasing complexity of HBM and future 3D architectures introduces additional challenges, such as thermal management. Consequently, the industry is shifting from simply adapting logic technologies to developing memory-specific solutions, including dedicated HKMG, RMG, and FinFET architectures tailored for the unique constraints of memory environments.

Furthermore, advances in memory-optimized design methodologies are imperative. Because memory technology and design are developed concurrently, accurate pre-layout modeling is essential for rapid design exploration. Memory design also continues to evolve from full-custom toward hybrid custom-digital methodologies. Building on this foundation, AI-native DTCO and STCO frameworks extend optimization across device, circuit, package, and system levels.

The convergence of Peri device innovation and memory-native design methodologies establishes a new AI Memory Platform paradigm. This paradigm enables workload-specific memory solutions built upon a common technology foundation, thereby transforming memory from a commodity into a strategic enabler of AI systems.

In recent years, two game changers have been reshaping IDM processes i.e. fab digitalization and advanced packaging. Digitalization links front-end modeling, device and circuit simulation, manufacturing analytics, and system-level validation into a continuous flow, accelerating learning and optimization. In parallel, advanced packaging, including panel-level packaging and wafer-to-wafer hybrid bonding, enables heterogeneous integration of logic, memory, power, sensors, and connectivity, allowing each application to combine the most suitable technologies for higher system performance. Building on these enablers, ST is pursuing three complementary technology trends.

• Silicon photonics provides fast, energy-efficient communication for AI server infrastructure.
• Expanding computing from advanced microcontrollers and edge AI to quantum computing.
• Sensing and actuation, based on imaging, MEMS, and power technologies, connect the physical and digital worlds for smarter automotive, industrial and personal electronics applications.

Full automation and robotics in manufacturing complements the new way of R&D in a fully virtual environment exploiting ST’s diversified technology portfolio. The IDM structure enables design-technology co-optimization and greater system-level flexibility.