Explore Short Courses

As AI systems scale from a single die to packages, boards, racks, and eventually warehouse-scale deployments, the dominant challenge increasingly shifts from compute alone to efficient data movement across every level of the system. This talk begins with a retrospective on how data-movement bottlenecks have evolved within the SoC and package, and how AMD’s architecture, SoC design, and advanced packaging strategies have adapted in response to rising bandwidth, latency, and energy demands. It then examines how modern AI workloads continue to expand these requirements, motivating a broader shift from a traditional component-centric view toward a system-level perspective in which interconnect, packaging, memory, and communication fabrics must be co-optimized. Building on that foundation, the talk frames the key design spaces of modern scale-in, scale-up, and scale-out systems, including the growing role of offload data-mover engines in sustaining performance and efficiency at scale. Finally, it discusses the opportunities and tradeoffs of extending optical communication more deeply into AI platforms, highlighting why device, packaging, and interconnect innovations are becoming central to overall system capability.

The relentless demand for energy-efficient computing, driven by AI and high-performance applications, continues to push logic technology beyond conventional scaling limits. The transition from planar FETs to FinFETs, and now to gate-all-around (GAA) transistors, has enabled substantial improvements in performance, power, area, and cost. However, extending this trajectory into the Angstrom era requires a holistic rethinking of device architecture, process integration, materials innovation, and design-technology co-optimization. This course reviews key enablers for advanced logic scaling, including RibbonFET (GAA) architecture, backside power delivery networks (BS-PDN), gate stack and contact integration, strain engineering, advanced patterning, and variability and reliability challenges. It further discusses emerging pathways toward 3D logic architectures, including complementary FET (CFET), and highlights the critical process-integration challenges required to translate these concepts into manufacturable technologies.

With the rapid growth of AI, the rising demand for real-time, intelligent applications has made edge AI computing a critical enabler of next-generation user experiences. This discussion reviews how process technology evolution—through innovative transistor architectures (from planar to FinFET to 2nm GAA) and continuous scaling—has historically driven improvements in mobile SoC PPAC (power, performance, area, and cost). As Moore’s Law faces increasing challenges & slowing down, we examine the role of design-technology co-optimization (DTCO) in sustaining its momentum and explore future opportunities with system-technology co-optimization (STCO) to further enhance PPAC in meeting future AI/Computing requirements.

Monolithic 3D integration is one of the vectors to advance device density of logic and memory integrated circuits. 3D integration requires vertical and lateral processing. In addition to deposition of tall stacks with alternating layers and high aspect ratio (HAR) etching, manufacturing of these structures will require a combination of lateral deposition and etching to achieve what can be called lateral film stacking. Lateral film stacking can be achieved by area selective ALD or alternating ALD and selective isotropic etching processes. Among the isotropic etching processes, ALE stands out as a method which enables etching of traditionally “hard to etch” materials with good etch control and top to bottom etch rate uniformity. We will discuss the mechanisms and performance of radical etching, continuous thermal etching and thermal ALE. One of the important figures of merit of the combined lateral deposition and etching processes is 3D edge-placement-error. We will introduce application examples for lateral stacking in advanced logic and memory devices and discuss the challenges the industry is facing.

Advanced packaging enables the high-performance computing essential for next-generation AI, but it also increases system complexity. As form factors expand and power densities rise, new system-level reliability challenges emerge—specifically regarding thermal management and thermomechanical stress. This tutorial discusses the various stages of package qualification and illustrates how TSMC’s component-level expertise can be leveraged to mitigate these system-level risks.

Stable, accurate, and precise signal delivery is at the heart of state-of-the-art superconducting quantum processors with tens of quantum bits. In today’s flagship architectures, the experimental setup—comprising cryogenics, wiring, filtering, and room-temperature electronics—is as critical as the design of the processor itself. Small disturbances or distortions of the control signal lead to catastrophic errors when executing quantum algorithms. As quantum processors grow, targeting more than 100,000 qubits in the next decade, scaling becomes a central challenge. The experimental setup increases in complexity and size, leading to larger signal distortions and poorer delivery. Moving electronics from room temperature to cryogenic environments has the potential of reducing wiring, thereby mitigating distortions and shrinking system size. However, new challenges arise, including stringent power constraints due to watt-level cooling capacities and unmodeled cryogenic physics, such as mobility shifts and more pronounced thermal effects.

Generative AI is changing the meaning of in-memory computing. For more than a decade, the field has been motivated by the mapping of neural-network weights to dense matrix-vector multiplications in memory arrays. This remains essential, but it is no longer sufficient. Modern AI systems are dominated by several memory objects with very different lifetimes: persistent model weights, transient activations, session-dependent KV caches, retrieval memories. This short course will build a memory-centric view of modern AI, contrasting cloud inference, where bandwidth, HBM capacity, batching and context management dominate, with edge inference, where energy, latency, privacy and non-volatile storage matter more. We will then examine how new model directions (long-context transformers, KV-cache compression, grouped or latent attention, state-space models, mixture-of-experts, and hybrid architectures) reshape the opportunity for volatile and non-volatile memories. The course will identify where classical analog and digital in-memory computing is powerful, where near-memory computation is more realistic, and where device innovation is needed. The goal is to define a roadmap toward energy-efficient generative AI in which memory is no longer only where data resides, but where intelligence is executed, stored, adapted and remembered.

Hyunbae Lee received the Ph.D. degree from Electronic and Electrical Engineering, POSTECH, Kyungbuk, Korea, in 2006. He joined SK hynix, Icheon, Korea, in 2011, where he is currently a Distinguished Engineer in the HBM advanced technology team since 2023. He was a leader of SERDES research group from 2011 to 2013, and team leader of advanced interface design team from 2019 to 2022 in SK hynix. Additionally he was an IEEE Asian Solid State Circuits Conference (ASSCC) committee member from 2015 to 2017 in wire-line session. His research interests include off-chip/on-chip signal integrity, low-power DRAM sense amplifier circuit, high-speed transceiver circuits with high performance clocking units, and HBM technologies. He has several patents, and papers of DRAM design and its related area especially for high speed designs.

In recent years, the scaling of conventional DRAM beyond the sub-10nm node has encountered significant barriers, primarily due to challenges in process integration and electrical performance. To address these issues, DRAM technology leveraging the oxide semiconductor Indium Gallium Zinc Oxide (InGaZnO) has garnered considerable attention. This innovative material exhibits ultra-low off-state leakage current characteristics, which are superior to those of traditional silicon, contributing to a reduction in power consumption, especially in future large-capacity DRAM.
Moreover, the structural transformation of DRAM cell transistors into a three-dimensional architecture such as 4F2 vertical channel transistors and 3D DRAM is achievable using InGaZnO as the channel material, thanks to its depositable nature. These advancements offer substantial opportunities for progress in DRAM technology, focusing on achieving higher bit density and lower power consumption through architectural modifications driven by cell transistor innovations.
In this presentation, we will explore the potential for technological breakthroughs in DRAM by implementing three-dimensional structuring of cell transistors using InGaZnO. This approach leads to the development of a novel DRAM technology termed Oxide-Semiconductor Channel Transistor DRAM (OCTRAM), aimed at achieving future high-density and low-power consumption DRAM technology.

As artificial intelligence (AI) reshapes computing and datacenter architectures, the demands placed on storage systems are evolving well beyond traditional storage system specifications. NAND flash, long the cornerstone of the storage hierarchy, now faces new system-level requirements driven by AI applications and cost-performance scaling pressure for traditional applications. At the same time, the boundary between memory and storage is blurring, calling for a fresh look at how NAND expands into the broader system hierarchy. In this talk, we will begin by revisiting how traditional NAND architecture characteristics map to vital storage system metrics. Next, we will examine how traditional storage system scaling (density, performance, and power) interacts with NAND technology scaling; explore how AI workloads are reshaping storage requirements in AI servers and discuss how these emerging demands interact with underlying storage technologies. Finally, we will highlight the expanding role of NAND beyond traditional bit storage — evolving from passive storage medium towards an active participant in the converging memory-storage hierarchy.

Spintronics is a field that harnesses both the charge and spin degrees of freedom of electrons to realize novel physical phenomena and advanced device functionalities. While long established in applications such as magnetic sensors, spintronics has more recently evolved into a cornerstone of next-generation memory technology, most notably through the advancement of Spin-Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM). This short course will provide an overview of recent breakthroughs in spintronics, with a focus on their integration into MRAM and emerging computational paradigms. Scaling challenges and device innovations in Spin-Transfer Torque MRAM (STT-MRAM) are first discussed. The session then transitions to Spin-Orbit Torque (SOT) mechanisms, examining the materials science and switching principles required to realize high-speed SOT-MRAM. Finally, the horizon of “beyond-memory” applications is explored, specifically focusing on probabilistic computing. By utilizing a probabilistic bit (p-bit) with a low-stability magnetic tunnel junction, spintronics offers a unique hardware platform to generate high-quality random streams, providing a promising path toward addressing complex computational problems in the AI era with high efficiency. Through this overview, the current R&D landscape is summarized, and a strategic outlook on the future of spintronic technologies in the semiconductor industry is provided.

Energy efficient AI data centers to support high performance computing, large language models and 500 billion parameter model algorithms require scaling high bandwidth density electrical and optical interconnections. The solutions take advantage of next generations of heterogeneous integration chiplet technology solutions using advanced packaging technologies. The need to manage large amounts of data for AI training and AI inference applications requires innovations for more efficient architectures, software and hardware solutions to support AI workloads and data. New architectures, digital twin models and simulations along with co-design for chiplet, 3D stacking and co-packaged interconnections are needed to support both scale out and scale up improvements in bandwidth density, energy efficiency and distance between chips to overcome bottle necks in compute, memory, and network communication links. This chiplet and advanced packaging technology review will address elements of importance including aspects of (1) Architecture / EDA / co-design ; (2) chiplets, packaging and components fabrication and test; (3) Chiplet and advanced package assembly, (4) Module level and rack level integration, power delivery, integration compatibility, thermal solutions and optical / electrical integration and (5) Reliability, serviceability and characterization.