Session 6: Circuit and Device Interaction Devices and Circuits for Neuromorphic and Stochastic Computing
Monday, December 4
Continental Ballroom 5
Co-Chairs: Shimeng Yu, Arizona State University
Runsheng Wang, Peking University
6.1 NeuroSim+: An Integrated Device-to-Algorithm Framework for Benchmarking Synaptic Devices and Array Architectures, P.-Y. Chen, X. Peng and S. Yu, Arizona State University
NeuroSim+ is an integrated simulation framework for benchmarking synaptic devices and array architectures in terms of the system-level learning accuracy and hardware performance metrics. It has a hierarchical organization from the device level (transistor technology and memory cell models) to the circuit level (synaptic array architectures and neuron periphery) and then to the algorithm level (neural network topologies). In this work, we study the impact of the “analog” eNVM non-ideal device properties and benchmark the trade-offs of SRAM, digital and analog eNVM based array architectures for online learning and offline classification.
6.2 Ferroelectric FET Analog Synapse for Acceleration of Deep Neural Network Training, M. Jerry, P.-Y. Chen*, J. Zhang, P. Sharma, K. Ni, S. Yu* and S. Datta, University of Notre Dame, * Arizona State University
We experimentally demonstrate a FeFET analog synapse based on partial polarization switching in HZO for acceleration of on-chip learning in neural networks. The symmetric 5-bit potentiation and depression characteristics of the FeFET synapse results in 90% accuracy for image recognition after training on the MNIST database. Further, the 75ns experimental programing pulse width improves training time on 1M images by 1000× compared to demonstrated RRAM devices while maintaining a 10× area advantage over SRAM.
6.3 Random Sparse Adaptation for Accurate Inference with Inaccurate Multi-level RRAM Arrays, A. Mohanty, X. Du, P.-Y. Chen, J.-s. Seo, S. Yu and Y. Cao, Arizona State University
This work proposes Random Sparse Adaptation (RSA) to efficiently recover the accuracy due to RRAM variations. RSA integrates a small, accurate on- chip memory with the main, inaccurate RRAM array. It completely eliminates Write of RRAM, achieving 10-100X speedup in MNIST and CIFAR-10, and >10% accuracy enhancement.
2:50 PM Coffee Break
6.4 Time-Dependent Variability in RRAM-based Analog Neuromorphic System for Pattern Recognition, J. Kang, Z. Yu, L. Wu, Y. Fang, Z. Wang, Y. Cai1*, Z. Ji, J. Zhang**, R. Wang, Y. Yang and R. Huang, Peking University, *National Key Laboratory of Science and Technology on Micro/Nano Fabrication, **Liverpool John Moores University
For the first time, this work investigated the time-dependent variability (TDV) in RRAMs and its interaction with the RRAM-based analog neuromorphic circuits for pattern recognition. It is found that even the circuits are well trained, the TDV effect can introduce non-negligible recognition accuracy drop during the operating condition. The impact of TDV on the neuromorphic circuits increases when higher resistances are used for the circuit implementation, challenging for the future low power operation. In addition, the impact of TDV cannot be suppressed by either scaling up with more synapses or increasing the response time and thus threatens both real-time and general-purpose applications with high accuracy requirements. Further study on different circuit configurations, operating conditions and training algorithms, provides guidelines for the practical hardware implementation.
6.5 Fast, Energy-Efficient, Robust, and Reproducible Mixed-Signal Neuromorphic Classifier Based on Embedded NOR Flash Memory Technology, X. Guo, F. Merrikh-Bayat, M. Bavandpour, M. Klachko, M. R. Mahmoodi, M. Prezioso, K. K. Likharev*, and D. B. Strukov, UC Santa Barbara, * Stony Brook University
We describe a prototype mixed-signal neuromorphic network with 100K+ floating-gate memory cells, redesigned from a commercial 180-nm NOR flash memory. The circuit can perform reliably and reproducibly classification of MNIST benchmark set images with ~95% fidelity and record-breaking sub- 1-μs time delay and sub-20 nJ energy consumption per pattern.
6.6 Design Guidelines of Stochastic Computing Based on FinFET: A Technology-Circuit Perspective, Y. Zhang, R. Wang, X. Jiang, Z. Lin, S. Guo, Z. Zhang, Z. Zhang and R. Huang, Peking University
Stochastic computing (SC) is a promising alternative to conventional deterministic computing, which enables ultralow power, high error-tolerance and massive parallelism, but not requiring new devices. In this paper, the feasibility of SC circuits based on state-of-the-art FinFET technology are investigated for the first time, with on-chip image processing application as an example. Practical technical issues are carefully examined, including static and transient device variations in 16/14nm FinFET. SC design optimization procedure is also proposed, which can considerably decrease its energy consumption without the penalty of accuracy. The results provide helpful guidelines for energy-efficient stochastic circuit design in new-paradigm computing.