IEDM

Session 5: Nano Device Technology 2D and Carbon Nanotube Devices

Monday, December 4
Continental Ballroom 4
Co-Chairs: Wei-Chih Chien, Macronix
Rossella Ranica, STMicroelectronics

1:35 PM
5.1 Gate-tunable memristors from monolayer MoS2 (Invited), V. K. Sangwan, H.-S. Lee, and M. C. Hersam, Northwestern University

We report here gate-tunable memristors based on monolayer MoS2 grown by chemical vapor deposition (CVD). These memristors are fabricated in a field-effect geometry with the channel consisting of polycrystalline MoS2 films with grain sizes of 3-5 microns. The device characteristics show switching ratios up to ~500, with the resistance in individual states being continuously gate-tunable by over three orders of magnitude. The resistive switching results from dynamically varying threshold voltage and Schottky barrier heights, whose underlying physical mechanism appears to be vacancy migration and/or charge trapping. Top-gated devices achieve reversible tuning of threshold voltage, with potential utility in non-volatile memory or neuromorphic architectures.

2:00 PM
5.2 First Demonstration of High Performance 2D Monolayer Transistors on Paper Substrates, S. Park and D. Akinwande, The University of Texas

In this work, we realize high performance transistors with graphene and MoS2 on commercially available paper substrates for the first demonstration. CVD graphene and MoS2 FETs feature record GHz operation and flexibility on paper, which indicates that high performance nanoelectronics on low-cost paper substrates for IoT and sensors is achievable.

2:25 PM
5.3 Room Temperature 2D Memristive Transistor with Optical Short-term Plasticity, X. Xie, J. Kang, Y. Gong*, P. M. Ajayan* and Kaustav Banerjee, University of California, Santa Barbara, *Rice University

A room temperature light-sensitive memristive transistor is demonstrated for the first time. This is achieved by creating a quantum dot superlattice structure fabricated on monolayer MoS2 where the quantum dots work as charge traps that induce memristive resistance, which can be modulated by a gate-induced electric field and exhibits light stimulation.

2:50 PM
5.4 Coexistence of volatile and non-volatile resistive switching in 2D h-BN based electronic synapses, Y. Shi, C. Pan, V. Chen*, N. Raghavan**, K. L. Pey**, F. M. Puglisi***, E. Pop*, H.-S. P. Wong*, M. Lanza, Soochow University, *Stanford University, **Singapore University, ***Università di Modena e Reggio Emilia

We fabricate electronic synapses using multilayer hexagonal boron nitride as switching layer. Their main advantage is that they show both volatile and non-volatile resistive switching depending on the programming stresses applied, which allows implementing short-term and long-term plasticity rules using a single device and without the need of complex architectures.

3:15 PM Coffee Break

3:40 PM
5.5 Scaling Carbon Nanotube CMOS FETs towards Quantum Limit (Invited), C. Qiu, Z. Zhang, and L.-M. Peng, Peking University

Owing to its ultra-thin body and high carrier mobility, semiconducting carbon nanotube (CNT) has been considered as an ideal channel material for future field-effect transistors (FETs) with sub 10 nm channel length. With well-designed device structure and when combined with graphene, we demonstrated high performance top-gated CNT FETs with gate length scaled down to 5nm. Scaling trend study reveals that sub-10 nm CNT CMOS FETs significantly outperform Si CMOS FETs with the same gate length but at much lower supply voltage Vds (0.4 V vs. 0.7 V), with an excellent sub- threshold slope swing (SS) of about 73mV/decade even with the gate length being scaled down to 5 nm. The 5 nm CNT FET begins to touch the quantum limit of a FET, and involves approximately only one electron when switching between on- state and off-state. These results show that CNT CMOS technology has the potential to go much further than that of Si towards quantum limit.

4:05 PM
5.6 Solution-Processed Carbon Nanotubes based Transistors with Current Density of 1.7 mA/µm and Peak Transconductance of 0.8 mS/µm, D. Zhong, M. Xiao, Z. Zhang, and L.-M. Peng, Peking University

High performance field-effect transistors are fabricated based on solution processed carbon nanotubes film. Via adopting stacked contacts and double gates, the FETs with gate length of 120 nm exhibit maximum drive current density of 1.7 mA/um and peak transconductance of 0.8 mS/um,which create a new record for CNT FETs.

4:30 PM
5.7 Benchmarking of Monolithic 3D Integrated MX2 FETs with Si FinFETs, T. Agarwal, A. Szabo*, M.G. Bardon, B. Soree, I. Radu, P. Raghavan, M. Luisier*, W. Dehaene, and M. Heyns, imec, *ETH, Zurich

In this paper, monolayer transition metal dichalcogenide (MX2) FETs are benchmarked with Si FinFET using energy-delay as figure-of-merits and a physical compact model. The model is validated with the help of both atomistic simulations and experimental data for different materials, without the use of any fitting parameter. Single-gate (SG) and double-gate (DG) MX2 FETs are compared from ON current, device capacitance and energy-delay perspective. DG MX2 FETs perform 25-30% faster than SG MX2 FETs for the same energy consumption in case of dominating wire load. WS2 DG FET shows both better energy and speed among chosen MX2 materials. However, in comparison to FinFET, WS2 DG FETs are shown to be ~ 35% slower, but more energy efficient. Therefore, to match FinFET’s performance with MX2 FETs, monolithic 3D integrated MX2 SG and DG FETs are explored. It is shown that 3-5 stacked WS2 DG FETs are needed to meet N3 FinFET performance.