Session 4: Modeling and Simulation Modeling and Simulation of Advanced Non-volatile Memory

Monday, December 4
Continental Ballroom 1-3
Co-Chairs: Masumi Satoh, Toshiba Corporation
Richard Williams, IBM

1:35 PM
4.1 Atomistic Investigation of the Electronic Structure, Thermal Properties and Conduction Defects in Ge-rich GexSe1-x Materials for Selector Applications, S. Clima, B. Govoreanu, K. Opsomer, A. Velea, N.S. Avasarala, W. Devulder, I. Shlyakhov*, G. L. Donadio, T. Witters, S. Kundu, L. Goux, V. Afanasiev*, G.S. Kar, G. Pourtois, imec, *University of Leuven

We investigate the electronic structure and defects of GexSe1-x materials at the atomic level, using full-layer-thickness (5nm) amorphous models. In Ge-rich GexSe1-x, the nature of the mobility gap defects is mostly related to miscoordinated Ge. The population/localization of mobility-gap states changes solely under the effect of electric field. Strong covalent bonds introduced by N doping in the material increase its thermal conductivity and crystallization temperature beyond 600C. C/N dopants are found to add/remove mobility-gap states in the doped systems. Our investigation sets guidelines for material design in view of improved electro-thermal device performance.

2:00 PM
4.2 Ab-initio Modeling of CBRAM Cells: from Ballistic Transport Properties to Electro-Thermal Effects, F. Ducry, A. Emboras, S. Andermatt, M. H. Bani-Hashemian, B. Cheng, J. Leuthold and M. Luisier, ETH Zurich

We present atomistic simulations of conductive bridging random access memory cells from first-principles combining density-functional theory and the Non-equilibrium Green’s Function formalism. Realistic device structures containing an atomic-scale filament have been constructed and their transport properties have been studied in the ballistic limit and in the presence of electron-phonon scattering.

2:25 PM
4.3 Fundamental Mechanism Behind Volatile and Non-Volatile Switching in Metallic Conducting Bridge RAM, N. Shukla, R. Krishna Ghosh, B. Grisafe and S. Datta, University of Notre Dame

In this work, we: (a) define an active-electrode selection criterion for non-volatile and volatile switching in metallic CBRAM; (b) simulate using MD+NEGF, the predicted volatile and non-volatile switching behavior in Ag/HfO2/Pt and Co/HfO2/Pt, along with the intrinsic switching time; (c) predict the switching behavior of other CBRAM active-electrodes, and corroborate with experiments.

2:50 PM
4.4 Modeling Disorder Effect of the Oxygen Vacancy Distribution in Filamentary Analog RRAM for Neuromorphic Computing, B. Gao, H. Wu, W. Wu, X. Wang, P. Yao, Y. Xi, W.Zhang, N. Deng, P. Huang*, X. Liu*, J. Kang*, H.-Y. Chen**, S. Yu***, and H. Qian, Tsinghua University, *Peking University, **GigaDevice Semiconductor Inc., ***Arizona State University

Physical mechanism of abrupt switching to analog switching transition is investigated using KMC simulation. A disorder-related model for Vo distribution is proposed with an order parameter to quantify the analog behaviors. Simulation results are verified by experiments performed on 1kb-RRAM-array. It is suggested that disordered Vo distribution is desired for analog switching.

3:15 PM Coffee Break

3:40 PM
4.5 Comprehensive Investigations on Charge Diffusion Physics in SiN-based 3D NAND Flash Memory through Systematical Ab initio Calculations, J. Wu, D. Han*, W. Yang, S. Chen**, X. Jiang* and J. Chen, Shandong University,*Chinese Academy of Sciences, **East China Normal University

Aiming at comprehensive understandings on the underlying physics of the charge diffusion in charge-trap (CT) 3D NAND flash memories, various hydrogen (H) and oxygen (O) incorporated defects in SiN CT layer are studied via ab initio calculations. It is found that, O atom incorporated defects are extremely shallow and could be the main reason of fast charge loss, while H atom incorporated defects should be the dominant traps in SiN CT layer. More importantly, though H passivation is effective to eliminate shallow traps, excessive H will generate other shallow traps on the contrary. Then, with further discussions on H bond stabilities, it is proposed that replacing H with Deuterium (D) could be an effective approach to suppress shallow trap generations during Write/Erase cycling and improve memory reliabilities.

4:05 PM
4.6 A Physics-based Quasi-2D Model to Understand the Wordline (WL) Interference Effects of Junction-Free Structure of 3D NAND and Experimental Study in a 3D NAND Flash Test Chip, W.-C. Chen, H.-T. Lue, C.-C. Hsieh, Y.-C. Lee, P.-Y. Du, T.-H. Hsu, K.-P. Chang, K.-C. Wang and C.-Y. Lu, Macronix International Co., Ltd

This paper provides a quasi-2D model simulating the surface potential variation inside a junction-free 3D NAND. It is clarified that the neighbor WL Vpass and Vt interference effects are the outcome of the surface potential continuity instead of WL fringe field effect. WL interference is studied in a 32Gb 16-layer single-gate vertical-channel (SGVC) 3D NAND Flash test chip. It is found that the far-neighbor WL cell also contributes to the WL interference, which could be suppressed by applying a lower BL sensing voltage. A practical WL iterating programming method can greatly cancel the WL interference effects and produce tight programmed Vt distribution for multi-level cell (MLC) operations.

4:30 PM
4.7 Temperature Activation of the String Current and its Variability in 3-D NAND Flash Arrays, D. Resnati, A.Mannara, G. Nicosia, G. M. Paolucci*, P. Tessariol*, A.L. Lacaita, A.S.Spinelli, and C. Monzio Compagnoni, Politecnico di Milano, *Micron Technology Inc.

After calibrating a TCAD model for current transport through the thin polysilicon channel of 3-D NAND Flash strings, we show for the first time that the variability in the polysilicon grain configuration in cell channel represents a nonnegligible source of statistical broadening for the array VT distribution when temperature is changed.