Session 39: Characterization, Reliability and Yield Advanced Reliability Characterization and Circuits
Wednesday, December 6
Imperial Ballroom A
Co-Chairs: Miaomiao Wang, IBM
Dimitri Linten, imec
39.1 Non-filamentary (VMCO) memory: a two- and three-dimensional study on switching and failure modes, U. Celano, C. Gastaldi, S. Subhechha, B. Govoreanu, G. Donadio, A. Franquet, T. Ahmad*, C. Detavernier*, O. Richard, H. Bender, L. Goux, G. S. Kar, P. van der Heide and W. Vandervorst, imec, *University of Ghent
In this work, for the first time, a set of two- and three-dimensional (3D) analysis techniques are combined to clarify the nature of resistive switching (RS) in state-of-the-art TiO2-based vacancy modulated conductive oxide (VMCO) memory.
39.2 Ultra Fast (<1 ns) Electrical Characterization of Self-heating Effect and Its Impact on Hot Carrier Injection in 14nm FinFETs, Y. Qu, X. Lin, J. Li, R. Cheng, X. Yu, Z. Zheng, J. Lu*, B. Chen and Y. Zhao, Zhejiang University, *Hunan University
We demonstrate electrical characterizations within sub- 1 ns to investigate the self-heating effect (SHE) in 14 nm FinFETs, for the first time. Thanks to the extremely fast I-V measurement speed (~500 ps), the heat generation and dissipation process in the transistor channel are precisely captured.
39.3 An Ultra-Dense Irradiation Test Structure with a NAND/NOR Readout Chain for Characterizing Soft Error Rates of 14nm Combinational Logic Circuits, S. Kumar, M. Cho*, L. Everson, H. Kim, Q. Tang, P. Mazanec, P. Meinerzhagen*, A. Malavasi*, D. Lake*, C. Tokunaga*, M. Khellah*, J. Tschanz*, S. Borkar*, V. De* and C. H. Kim, University of Minnesota, *Intel Corporation
This paper describes a 14nm test chip employing a novel NAND/NOR readout chain for characterizing soft error rate (SER) in combinational logic gates. The proposed circuit is compact, has a scalable architecture and incurs minimal area overhead. Different gate configurations (device size, threshold voltage, fan-out and chain length) were implemented in the 14nm test-chip and irradiated under a neutron beam to collect a massive amount of statistical data. Radiation data captures, for the first time, the impact of various circuit parameters on combinational logic SER in 14nm tri-gate technology.
39.4 Investigation of Statistical Retention of Filamentary Analog RRAM for Neuromophic Computing, M. Zhao, H. Wu, B. Gao, Q. Zhang, W. Wu, S. Wang, Y. Xi, D. Wu, N. Deng, S. Yu*, H.-Y. Chen**, and H. Qian, Tsinghua University, *Arizona State University, **GigaDevice Semiconductor Inc.
The retention requirements of analog RRAM for neuromorphic computing applications are quite different from conventional RRAM for memory applications. Meanwhile, filamentary analog RRAM exhibits different retention behavior in comparison to strong-filament RRAM. For the first time, the statistical behaviors of read current noise and retention in a 1Kb filamentary analog RRAM array are investigated in this work. The conductance distribution of different levels is found to change with time, and the physical mechanism of the retention degradation is elucidated. From the experimental data, a compact model is developed in order to predict the statistical conductance evolution, which can effectively evaluate the impact of read noise and retention degradation in neuromorphic computing systems.
39.5 Combatting IC Counterfeiting Using Secure Chip Odometers (Invited), N. E. Can Akkaya, B. Erbagci, and K. Mai, Carnegie Mellon University
To combat IC counterfeiting, a secure chip odometer was designed to provide ICs with both a secure gauge of use/age and an authentication of provenance enabling simple, secure, robust differentiation between genuine and counterfeit parts. The secure chip odometers employ chained one-shot binary aging elements (BAEs) that use intentional accelerated device aging to measure use and age of the chip. A prototype secure odometer was taped out on a 1.2mm x 1.7mm testchip in a 65nm bulk CMOS process as a proof-of-concept.