IEDM

Session 38: Memory Technology STT-MRAM

Wednesday, December 6
Continental Ballroom 6
Co-Chairs: Luc Thomas, TDK-Headway Technologies
Gwan-Hyeob Koh, Samsung Electronics

1:35 PM
38.1 Threshold Switching Selector and 1S1R Integration Development for 3D Cross-point STT-MRAM, H. Yang, X. Hao, Z. Wang, R. Malmhall, H. Gan, K. Satoh, J. Zhang, D. H. Jung, X. Wang, Y. Zhou, B. K. Yen and Y. Huai, Avalanche Technology

We present a bi-directional threshold switching selector and integrated one selector/one perpendicular MTJ (1S1R) device. The selector shows above 1E+7 On/Off ratio, 1 pA leakage current, 0.3 V threshold voltage, and fast speed (10 ns). Switching operations between “AP” and “P” state have been demonstrated for the 1S1R STT-MRAM device.

2:00 PM
38.2 MRAM: Enabling a Sustainable Device for Pervasive System Architectures and Applications (Invited), S. Kang and C. Park, Qualcomm Technologies, Inc.

MRAM, specifically, perpendicular spin-transfer-torque (STT) MRAM, has reached a stage to serve early adopters. With its unique attributes and tunability, MRAM can create desirable system differentiations which were not possible due to inherent limitations of various memories. MRAM is poised for a unified memory subsystem that can revamp the archi-tectures of emerging ultra-low-energy systems such as Inter-net-of-Things (IOT) and wearable devices. Furthermore, MRAM has a potential to transform computing-centric archi-tectures at more advanced nodes.

2:25 PM
38.3 Key Parameters Affecting STT-MRAM Switching Efficiency and Improved Device Performance of 400ºC-Compatible p-MTJs, G. Hu, M. G. Gottwald, Q. He, J. H. Park, G. Lauer, J. J. Nowak, S. L. Brown, B. Doris, D. Edelstein, E. R. Evarts, P. Hashemi, B. Khan, Y. H. Kim, C. Kothandaraman, N. Marchack, E. J. O’Sullivan, M. Reuter, R. P. Robertazzi, J. Z. Sun, T. Suwannasiri, P. L. Trouilloud, Y. Zhu and D. C. Worledge, IBM-Samsung MRAM Alliance, IBM TJ Watson Research Center

We report the impact of four key parameters on switching efficiency of STT-MRAM devices with perpendicular magnetic anisotropy: device size, device resistance-area product (RA), blanket film Gilbert damping constant (α), and process temperature. Performance degradation observed in 400ºC-processed devices was eliminated by optimizing the perpendicular magnetic tunnel junction (p-MTJ) materials. Furthermore, 400ºC-compatible double MTJs were developed for the first time and showed 1.5x improvement in switching efficiency compared to single MTJs with identical free layers.

2:50 PM
38.4 Probing magnetic properties of STT-MRAM devices down to sub-20 nm using Spin-Torque FMR, L. Thomas, G. Jan, S. Le, S. Serrano-Guisan, Y.-J. Lee, H. Liu, J. Zhu, J. Iwata-Harms, R.-Y. Tong, S. Patel, V. Sundar, D. Shen, Y. Yang, R. He, J. Haq, Z. Teng, V. Lam, P. Liu, Y.-J. Wang, T. Zhong, and P.-K. Wang
TDK- Headway Technologies, Inc.

Scaling STT-MRAM cells beyond 1X technology node will require MTJ devices smaller than 30 nm. For such small sizes, process-induced damage becomes a primary factor of device performance. A robust method of assessing magnetic properties of sub-30 nm devices is thus needed. Here we report measurements of the anisotropy field HK down to 20 nm devices using ST-FMR. We show that HK increases for decreasing sizes. The interfacial anisotropy field exceeds 23 kOe, leading to HK larger than 13 kOe for 20 nm devices under optimal process conditions. Using insight from micromagnetic simulations, we develop a simple model to fit HK size dependence, allowing us to quantify magnetic edge damage for various process conditions.

3:15 PM
38.5 Novel approach for nano-patterning magnetic tunnel junctions stacks at narrow pitch: A route towards high density STT-MRAM applications, V. D. Nguyen, P. Sabon, J. Chatterjee, L. Tille , P. Veloso Coelho, S. Auffret, R. Sousa, L. Prejbeanu, E. Gautier, L. Vila and B. Dieny, Grenoble Alpes University

Etching magnetic tunnel junction (MTJ) cells at low dimension and very dense pitch remains challenging for high density STT-MRAM. This paper demonstrates a novel scalable approach for MTJ nano-patterning at very narrow pitch (pitch=1.5F, F=MTJ dot diameter) by growing the MTJ material on pre-patterned conducting non-magnetic pillars without post-deposition etching.

3:40 PM
38.6 Solving the BEOL compatibility challenge of top-pinned magnetic tunnel junction stacks, J. Swerts, E. Liu, S. Couet, S. Mertens, S. Rao, W. Kim, K. Garello, L. Souriau, S. Kundu, D. Crotti, F. Yasin, N. Jossart, S. Sakhare, T. Devolder*, S. Van Beek, B. O’Sullivan, S. Van Elshocht, A. Furnemont, G.S. Kar, imec, * Univ. Paris-Sud, Univ. Paris-Saclay

We report for the first time 400°C compatible top- pinned perpendicular magnetic tunnel junction stacks. High TMR of 180% at RA 9 Ohm.µm2 is demonstrated. A new synthetic ferromagnetic stack pinning layer design is used to demonstrate free layer off-set control and low current switching in 30nm CD devices.