Session 37: Process and Manufacturing Technology Advanced Transistor Technologies

Wednesday, December 6
Continental Ballroom 5
Co-Chairs: Han-Su Oh, Samsung
Sandy Liao, Intel

1:35 PM
37.1 Sub-nm EOT Ferroelectric HfO2 on p+Ge with Highly Reliable Field Cycling Properties, X. Tian, L. Xu, S. Shibayama, T. Nishimura, T. Yajima, S. Migita* and A. Toriumi, The University of Tokyo, *National Institute of Advanced Industrial Science & Technology (AIST)

5-nm-thick ferroelectric Y-doped HfO2 was intensively studied. The thickness dependence of ferroelectric properties indicates that stable ferroelectric characteristics are maintained down to 5-nm-thick by taking care of doping and capping effects. Furthermore, the cycling performance shows no wake-up behavior, no obvious degradation after 108 cycles. These results not only enable us to use ferroelectric HfO2 for practical application, but also point out intrinsic properties in ultrathin ferroelectric HfO2 film from materials science point of view.

2:00 PM
37.2 A Comparative Study of Strain and Ge Content in Si1-xGex Channel using Planar FETs, FinFETs, and Strained Relaxed Buffer Layer FinFETs, C. H. Lee, S. Mochizuki, R. G. Southwick III, J. Li, X. Miao, R. Bao, T. Ando, R. Galatage*, S. Siddiqui*, C. Labelle*, A. Knorr*, J. H. Stathis, D. Guo, V. Narayanan, B. Haran, and H. Jagannathan, IBM Research and *GLOBALFOUNDRIES Inc.

Strained Si1-xGex channel pFinFETs and planar pFETs are fabricated on a strain relaxed buffer virtual substrate to comparatively study the electrical impact of strain and Ge content in the Si1-xGex channel. By comparing the transistor electrical properties of Si1-xGex pFETs on SRB with Si1-xGex pFETs on Si substrate, we successfully decouple the influence of strain and Ge content in the Si1-xGex channel on device performance such as gate stack quality, reliability, and carrier transport. Based on these understandings, dual channel Si/Si1-xGex FinFETs on the SRB with the optimized surface orientation is proposed to further improve the device performance.

2:25 PM
37.3 High Performance and Reliable Strained SiGe PMOS FinFETs Enabled by Advanced Gate Stack Engineering (Invited), P. Hashemi, T. Ando, E. A. Cartier, K.-L. Lee, J. Bruley, C.-H. Lee, and V. Narayanan, IBM T.J. Watson Research Center

Gate-stack engineering is critical to enable high- performance high-Ge-content strained-SiGe FinFETs. In this paper, key process details to achieve optimized gate-first and RMG gate-stacks are disclosed and devices with near-ideal SS, excellent NBTI, mobility and transconductance at scaled-EOTs are presented. Aggressively-scaled Fins with WFIN=6.4nm and excellent short-channel characteristics are also demonstrated.

2:50 PM
37.4 Vertically Stacked Gate-All-Around Si Nanowire Transistors: Key Process Optimizations and Ring Oscillator Demonstration, H. Mertens, R. Ritzenthaler, V. Pena*, G. Santoro1, K. Kenis, A. Schulze, E. D. Litta, S. A. Chew, K. Devriendt, T. Chiarella, S. Demuynck, D. Yakimets, D. Jang, A. Spessot, G. Eneman, A. Dangol, P. Lagrain, H. Bender, S. Sun*, M. Korolik*, D. Kioussis*, M. Kim*, K-.H. Bu*, S. C. Chen*, M. Cogorno*, J. Devrajan*, J. Machillot*, N. Yoshida*, N. Kim*, K. Barla, D. Mocuta, N. Horiguchi, imec, *Applied Materials

We report on CMOS-integrated vertically stacked gate-all-around Si nanowire MOSFETs with in-situ doped source-drain stressors and dual work function metal gates. We describe process improvements for shallow trench isolation, source-drain epitaxy, nanowire/nanosheet release, and NMOS VTH tuning. In addition, we report functional ring oscillators.

3:15 PM
37.5 First Vertically Stacked GeSn Nanowire pGAAFETs with Ion=1850µA/µm (VOV=VDS=-1V) on Si by GeSn/Ge CVD Epitaxial Growth and Optimum Selective Etching, Y.-S. Huang, F.-L. Lu, Y.-J. Tsou, C.-E. Tsai,; C.-Y. Lin, C.-H. Huang, and C.W. Liu, National Taiwan University

We demonstrate the first stacked GeSn pGAAFETs. Good crystalline quality and strong PL are achieved from CVD-grown stacked GeSn layers. With Ge barriers as sacrificial layers and optimum ultrasonic-assisted H2O2 etching technique, the stacked Ge0.9Sn0.1 channel with LCH=60nm has record high Ion=1850uA/um among all published GeSn pFETs with SS=88mV/dec.