Session 33: Process and Manufacturing Technology Ge Channel Devices

Wednesday, December 7, 1:30 p.m.
Continental Ballroom 4
Co-Chairs: Mitsuhiro Togo, GLOBALFOUNDRIES
Mariam Sadaka, SOITEC

1:35 PM
33.1 Record High Mobility (428cm2/V-s) of CVD-grown Ge/Strained Ge0.91Sn0.09 /Ge Quantum Well p-MOSFETs, Y.-S. Huang, C.-H. Huang, F.-L. Lu, C.-Y. Lin, H.-Y. Ye, I-H. Wong, S.-R. Jan, H.-S. Lan, C. W. Liu, Y.-C. Huang*, H. Chung*, C.-P. Chang*, S. Chu* and S. Kuppurao*, National Taiwan University, *Applied Materials Inc

By optimizing the cap thickness, the record high mobility (428cm2/V-s) of the CVD grown-GeSn QW p-MOSFETs is achieved with low thermal budget of 400oC. The ~7% mobility enhancement on <110> channel direction is observed using external transverse uniaxial tensile strain of ~0.11% due to the reduction of effective mass. The mobility of GeSn QW p-MOSFETs increases with decreasing temperature at low Ninv, indicating that phonon scattering is dominated, different from bulk Ge p-MOSFETs. The normalized noise power density of GeSn p-MOSFETs decreases with increasing Ge cap thickness, reportedly for the first time, indicating that the carrier number fluctuation and correlated mobility fluctuation can be reduced when the carriers are away from interface.

2:00 PM
33.2 Processing and Characterization of Si/Ge Quantum Dots (Invited), S.Miyazaki, K. Makihara, A. Ohta and M. Ikeda, Nagoya University

We have demonstrated high density formation of Si quantum dots with Ge core on thermally-grown SiO2 with control of highly-selective CVD. Through luminescence measurements, we have reported characteristic carrier confinement and recombination properties in the Ge core. Also, an impact of P delta-doping to the Ge core on the properties were shown.

2:25 PM
33.3 High Performance and Reliability Ge Channel CMOS with a MoS2 Capping Layer, J. Li, S. Xie, Z. Zheng, Y. Zhang, R. Zhang, M. Xu and Y. Zhao, Zhejiang University

High performance Ge CMOS with quantum well- structured channels has been successfully realized using a single MoS2 capping layer. Thanks to a large valence band offset (0.43 eV) and conduction band offset (0.5 eV) between the 2-layers-thick MoS2 and the Ge substrate, both holes and electrons within the Ge p- and n-MOSFETs are confined into Ge channels and the scattering due to the traps in gate stack is suppressed effectively. As a result, the MoS2/Ge p- and n- MOSFETs exhibit much improved hole and electron mobility, as well as the improved device reliability behaviors.

2:50 PM
33.4 Si-passivated Ge nMOS Gate Stack with Low DIT and Dipole-induced Superior PBTI Reliability using 3D-compatible ALD Caps and High-pressure Anneal, H. Arimura, D. Cott, R. Loo, W. Vanherle, Q. Xie*, F. Tang*, X. Jiang*, J. Franco, S. Sioncke, L.- Å Ragnarsson, E. Chiu**, X. Lu***, J. Geypen, H. Bender, J. Maes*, M. Givens*, A. Sibaja-Hernandez, K. Wostyn, G. Boccardi, J. Mitard, N. Collaert and D. Mocuta, imec, *ASM Belgium, **Poongsan, ***Nanyang Technological University

We have demonstrated a 3D-compatible Si-passivated Ge nMOS gate stack solution with improved PBTI reliability and electron mobility. While ALD LaSiO insertion at HfO2/SiO2 interface improves PBTI reliability thanks to the dipole-induced band engineering, its combination with high-pressure anneal reduces Dit to 5×10^10 cm-2eV-1 around midgap and improves mobility.

3:15 PM
33.5 High Performance Complementary Ge Peaking FinFETs by Room Temperature Neutral Beam Oxidation for Sub-7 nm Technology Node Applications, Y.-J. Lee, T.-C. Hong*, F.-K. Hsueh, P.-J. Sung, C.-Y. Chen*, S.-S. Chuang*, T.-C. Cho*, S. Noda**, Y.-C. Tsou***, K.-H. Kao***, C.-T. Wu, T.-Y. Yu, Y.-L. Jian, C.-J. Su, Y.-M. Huang, W.-H. Huang, B.-Y. Chen, M.-C. Chen, K.-P. Huang^, J.-Y. Li^^, M.-J. Chen^^^, Y. Li^, S. Samukawa**, W.-F. Wu, G.-W. Huang, J.-M. Shieh, T.-Y. Tseng*, T.-S. Chao*, Y.-H. Wang*** and W.-K. Yeh, National Nano Device Laboratories, *National Chiao Tung University, **Tohoku University, ***National Cheng Kung University, ^Industrial Technology Research Institute, ^^National Taiwan University

Ge peaking n- and p-FinFETs have been demonstrated by adopting neutral beam etching (NBE) and anisotropic neutral beam oxidation (NBO) processes. The irradiation-free NB processes not only suppress surface roughness but also guarantee low defect generation on the etched Ge surface. The fabricated Ge peaking FinFETs possess several unique features: (1) A peaking fin configuration with a 6-nm top-gate formed by an anisotropic NBO process at room temperature (RT). (2) Nearly defect-free three dimensional channel surfaces by NB processes. (3) ION and Gm improvement by NB processes as compared to that by conventional inductively coupled plasma (ICP) reactive ion etching. (4) Recorded high ION/IOFF ratio and low subthreshold swing (S.S. ~ 70 mV/dec) of Ge n- FinFETs. (5) Excellent immunity for short channel effect of Ge FinFETs.

3:40 PM
33.6 High Performance Ge Junctionless Gate-all-around NFETs with Simultaneous Ion =1235 µA/µm at VOV=VDS=1V, SS=95 mV/dec, high Ion/Ioff=2×106, and Reduced Noise Power Density using S/D Dopant Recovery by Selective Laser Annealing, I-H. Wong, F.-L. Lu, S.-H. Huang, H.-Y. Ye, C.-T. Lu, J.-Y. Yan, Y.-C. Shen,Y.-J. Peng, H.-S. Lan and C. W. Liu, National Taiwan University

The low channel doping concentrations of 1.2E19 cm-3 to deplete the channel and the high S/D doping of 1.2E20 cm-3 to reduce the S/D resistance are achieved simultaneously by selective laser annealing on epi-Ge on SOI. The device with Wfin down to 7 nm has Ion = 1146 mA/mm, Ion/Ioff = 2E6, and SS = 95 mV/dec. The Ion can be boost to 1235 mA/mm with tensile strain. The self-heating effect is responsible in part for high Ion, because the high device temperature can reduce the dominant impurity scattering. The lower low frequency noise is observed with junctionless gate-all-around FETs than planar inversion mode devices.