Session 31: Modeling and Simulation Simulations of Nano-devices

Wednesday, December 6
Continental Ballroom 1-3
Co-Chairs: Mathieu Luisier, ETH Zurich
Viktor Sverdlov, TU Wien

9:05 AM
31.1 Time-resolved quantum transport for optoelectronics (Invited), F. Michelini, K. Beltako, M. Bescond, N. Cavassilas and L. Raymond, Aix Marseille University, University Toulon, IM2NP

We investigate time-resolved energy currents in a molecular optoelectronic junction made of two donors and an acceptor sandwiched between two electrodes and excited by a Gaussian femtosecond laser pulse. Features of the direct energy currents are thus correlated to the intra-molecular structure.

9:30 AM
31.2 Computational Study of Gate-Induced Drain Leakage in 2D-Semiconductor Field-Effect Transistors, J. Kang, W. Cao, A. Pal, S. Pandey*, S. Kramer*, R. Hill*, G. Sandhu*, and K. Banerjee, University of California, Santa Barbara, *Micron Technology, Inc.

Gate-induced-drain-leakage (GIDL) in 2D FETs is evaluated for the first time using a novel quantum transport methodology. GIDL is a key issue in access transistors, and our results establish the advantages of certain 2D semiconductors in greatly reducing GIDL and thereby support use of such materials in future memory technologies.

9:55 AM
31.3 How to Derive the Highest Mobility from 2D FETs – A First-Principle Study, A. Pal, W. Cao, J. Kang, and K. Banerjee, University of California Santa Barbara

A comprehensive mobility modeling framework for 2D-semiconductor FETs is developed for the first time. The framework is applied to study the impact of synthesis technology, defect concentration, electric field, and channel/dielectric materials on the mobility and guidelines are provided to both process and device engineers on designing FETs with maximized mobility.

10:20 AM
31.4 A Unified Surface Potential Based Physical Compact Model for Both Unipolar and Ambipolar 2D-FET: Experimental Verification and Circuit Demonstration, L. Wang, Y. Li, X. Feng, K.-W. Ang, X. Gong, A. Thean, G. Liang, National University of Singapore

A unified surface potential based physical compact model for both unipolar and ambipolar 2D-FET is developed and verified by device measurements. It included the influence of extensive disorder effects on transport. This compact model is implemented in Verilog-A for evaluating the possibility of digital and RF applications with 2D-FETs.

10:45 AM
31.5 Quantitative Model for Switching Asymmetry in Perpendicular MTJ: A Material-Device-Circuit Co-Design, D. Datta, H. Dixit, S. Agarwal, A. Dasgupta*, M. Tran**, D. Houssameddine**, Y. S. Chauhan*, D. Shum**, and F. Benistant**, GLOBALFOUNDRIES Engineering Pvt. Ltd., *Indian Institute of Technology, **GLOBALFOUNDRIES Singapore Pte. Ltd.

A physics based switching model for p-MTJ device is presented by combining 4×4 tunnelling conductance matrix derived using NEGF formalism and 4×4 ferromagnetic conductance matrix derived from Valet-Fert equation. It provides qualitative and quantitative agreement with switching voltages in spin torque experiments observed in IBM, Everspin and GLOBALFOUNDRIES hardware data.

10:45 AM
31.5 Deep Insights into Dielectric Breakdown in Tunnel FETs with Awareness of Reliability and Performance Co-Optimization, Q. Huang, R. Jia, J. Zhu,. Lv, J. Wang, C. Chen, Y. Zhao, R. Wang, W. Bu*, W. Wang*, J. Kang*, K. Hua*, H. Wu*, S. Yu*, Y. Wang and R. Huang, Peking University, *Semiconductor Manufacturing International Corporation

The gate dielectrics reliability in Tunnel FETs (TFETs) has been thoroughly investigated for the first time, which is found to be the dominant device failure mechanism compared with bias temperature ins tability degradation, and is much worse than MOSFETs with the same gate stacks due to a new stronger localized dielectric field peak at gate/source overlap region. The non-uniform electric field of dielectric in TFET also leads to the different mechanisms between soft breakdown and hard breakdown failure. Moreover, dielectric-field-associated parameters are discussed in detail, showing an intrinsic trade-off between dielectrics reliability and device performance optimization caused by the positive correlation between dielectric field and source junction field. A new robust design consideration is further proposed for reliability and performance co-optimization, which is experimentally realized by a new TFET design with both dramatically improved performance and reliability, indicating its great potentials for ultralow-power applications.

11:10 AM
31.6 Comprehensive Model for Progressive Breakdown in nFETs and pFETs, S. Lombardo, E. Wu* and J.Stathis*, CNR-IMM, IBM Research

Through comparison with a large data set, we show that progressive breakdown (PBD) of gate oxides is described by a physical model coupling carrier energy dissipation to electromigration producing the PBD growth. Dependence on temperature, voltage, carrier type, oxide thickness, and the statistics are well described in a consistent framework.

11:35 AM
31.7 A Fundamental AC TDDB Study of BEOL ELK Dielectrics in Advanced Technology, M.N. Chang, Y.-H. Lee, S.Y. Lee and Y.S. Huang, TSMC

In this study, we thoroughly investigated AC TDDB in BEOL extreme low-k (ELK) dielectric in 10nm technology. We demonstrated that AC TDDB of ELK dielectric has better median-time-to-failure (MTTF) and also much tighter Weibull distribution than constant voltage stress (DC TDDB). In unipolar AC TDDB stress, a very significant recovery process was observed. Through the capacitance recovery analysis, the capture and emission time constants for ELK were found to be  10-3 and ~10-8 seconds respectively, which implies that there is low probability of charge trapping when the stress period is as fast as 10-3 seconds; meanwhile the charge detrap happens continuously when the stress period is lower than 10-8 seconds. As a result, the unipolar AC TDDB lifetime increased with increasing frequency. In addition, the unipolar AC TDDB improvement shows a power law dependence on the duty ratio due to a very significant charge trap/detrap effect. This is further validated through a physics-based simulation. On the other hand, bipolar AC stress caused the ion diffusion to be accompanied by the backflow Cu ion drift, thus extending the defect growth rate and improving the TDDB performance. However, no significant frequency and duty ratio dependence on the bipolar AC to DC ratio was found because the critical Cu ion concentration was constrained by the ion diffusion mechanism. This study suggests that actual circuit operation in the AC condition should have a much longer back-end TDDB lifetime than the projection by DC stress assessment for BEOL ELK dielectrics.

12:00 PM
31.8 Sustainable Electronics for Nano-Spacecraft in Deep Space Missions, D.-I. Moon, J.-Y. Park*, J.-W. Han, G.-J. Jeon*, J.-Y. Kim*, J. Moon*, M.-L. Seol, C. K. Kim*, H. C. Lee*, M. Meyyappan and Y.-K. Choi*, NASA Ames Research Center, *KAIST

On-the-fly self-healing devices are experimentally demonstrated for sustainable space electronics. High temperature generated by Joule heating in gate electrode provides on-chip annealing of ionizing radiation, hot carrier, and tunneling damages. With self-healing process, highly scaled SiNW GAA FETs show long-term reliability in Logic, floating body DRAM, and Flash memory. Thermally isolated gate structure is proposed to enhance self-healing effects.