Session 31: Characterization, Reliability and Yield Reliability Modeling and Characterization of Dielectrics and Interfaces

Wednesday, December 7, 9:00 a.m.
Imperial Ballroom A
Co-Chairs: Chen Jiezhi, Shandong University
Chris H. Kim, University of Minnesota

9:05 AM
31.1 Engineering the Electronic Defect Bands at the Si1-xGex/IL Interface: Approaching the Intrinsic Carrier Transport in Compressively-Strained Si1-xGex pFETs, C.H. Lee, R. Southwick III and H. Jagannathan, IBM Research

We identify the existence of electronic defect levels close to the Si1-xGex band edges associated with the Ge surface concentration at the Si1-xGex/IL interface (0 < x < 0.5). These electronic defects act as carrier scattering centers severely degrading the channel mobility and modulate the device threshold voltage. By successfully eliminating the electronic defects states at the Si1-xGex/IL interface, through control of the Ge surface concentration, high channel carrier mobility over wide charge densities in compressively-strained Si1-xGex channel pFETs is demonstrated. For the first time, the dominant scattering mechanisms for hole mobility in Si1-xGex channel pFETs are investigated to understand the carrier transport physics.

9:30 AM
31.2 Acceptor-like Trap Effect on Negative-Bias Temperature Instability (NBTI) of SiGe pMOSFETs on SRB, G. Jiao, M. Toledano-Luque, K.-J. Nam, N. Toshiro, S.-H. Lee, J.-S. Kim, T. Kauerauf, EA. Chung, D. Bae, G. Bae, D.-W. Kim and Kihyun Hwang, Samsung Electronics

In this work, the oxide electric field (Eox) reduction caused by negatively charged traps is proposed to explain the robustness of SiGe pMOSFETs to negative gate bias temperature instability (NBTI) stress. The high density of negatively charged acceptor-like traps close to the SiGe valance band (Ev) lowers the Eox and reduces the NBTI degradation at fixed overdrive. We demonstrate that trap engineering can be exploited to meet aggressive reliability requirements. Furthermore, it is predicted that there are no reliability issues in the SiGe pMOSFETs comparing with the Si counterparts.

9:55 AM
31.3 Fast-Trap Characterization in Ge CMOS Using Sub-1 ns Ultra-Fast Measurement System, X. Yu, B. Chen, R. Cheng, Y. Qu, J. Han, R. Zhang and Y. Zhao, Zhejiang University

Ge p- and n-MOSFETs with Al2O3/GeOx/Ge gate stack were fabricated and characterized using a novel sub-1 ns ultra-fast measurement system. Devices operation under the conditions, that applying Vg with the ultra-fast rise edge down to less than 1 ns are confirmed. It is found that the current degradation within the first 10 ns is much more significant than that from 100 ns to longer time due to the fast trapping effect. In additions, the trap density distributions in Ge MOSFETs inside Ec and Ev are measured and calculated.

10:20 AM
31.4 Predictive As-grown-Generation (A-G) Model for BTI-induced Device/circuit Level Variations in Nanoscale Technology Nodes, R. Gao, Z. Ji, S. Hatta*, J. Zhang, J. Franco**, B. Kaczer**, W. Zhang, M. Duan, S. De Gendt**, D. Linten**, G. Groeseneken**, J. Bi*** and M. Liu***, Liverpool J. Moores University, *University of Malaya, **imec, ***Institute of Microelectronics of the Chinese Academy of Sciences

A new model for assessing NBTI and PBTI induced time-dependent variability under practical operation workloads is proposed. The model is based on a realistic understanding of different types of defects and has excellent predictive capability, as validated by comparison with experimental data. In addition, a new fast wafer- level test scheme for parameter extraction is developed, reducing test time to 1 hour/device and significantly improving the efficiency for variability tests of nanoscale devices. The model is implemented into a commercial simulator and its applicability for circuit level simulation is demonstrated.

10:45 AM
31.5 Deep Insights into Dielectric Breakdown in Tunnel FETs with Awareness of Reliability and Performance Co-Optimization, Q. Huang, R. Jia, J. Zhu,. Lv, J. Wang, C. Chen, Y. Zhao, R. Wang, W. Bu*, W. Wang*, J. Kang*, K. Hua*, H. Wu*, S. Yu*, Y. Wang and R. Huang, Peking University, *Semiconductor Manufacturing International Corporation

The gate dielectrics reliability in Tunnel FETs (TFETs) has been thoroughly investigated for the first time, which is found to be the dominant device failure mechanism compared with bias temperature ins tability degradation, and is much worse than MOSFETs with the same gate stacks due to a new stronger localized dielectric field peak at gate/source overlap region. The non-uniform electric field of dielectric in TFET also leads to the different mechanisms between soft breakdown and hard breakdown failure. Moreover, dielectric-field-associated parameters are discussed in detail, showing an intrinsic trade-off between dielectrics reliability and device performance optimization caused by the positive correlation between dielectric field and source junction field. A new robust design consideration is further proposed for reliability and performance co-optimization, which is experimentally realized by a new TFET design with both dramatically improved performance and reliability, indicating its great potentials for ultralow-power applications.

11:10 AM
31.6 Comprehensive Model for Progressive Breakdown in nFETs and pFETs, S. Lombardo, E. Wu* and J.Stathis*, CNR-IMM, IBM Research

Through comparison with a large data set, we show that progressive breakdown (PBD) of gate oxides is described by a physical model coupling carrier energy dissipation to electromigration producing the PBD growth. Dependence on temperature, voltage, carrier type, oxide thickness, and the statistics are well described in a consistent framework.

11:35 AM
31.7 A Fundamental AC TDDB Study of BEOL ELK Dielectrics in Advanced Technology, M.N. Chang, Y.-H. Lee, S.Y. Lee and Y.S. Huang, TSMC

In this study, we thoroughly investigated AC TDDB in BEOL extreme low-k (ELK) dielectric in 10nm technology. We demonstrated that AC TDDB of ELK dielectric has better median-time-to-failure (MTTF) and also much tighter Weibull distribution than constant voltage stress (DC TDDB). In unipolar AC TDDB stress, a very significant recovery process was observed. Through the capacitance recovery analysis, the capture and emission time constants for ELK were found to be  10-3 and ~10-8 seconds respectively, which implies that there is low probability of charge trapping when the stress period is as fast as 10-3 seconds; meanwhile the charge detrap happens continuously when the stress period is lower than 10-8 seconds. As a result, the unipolar AC TDDB lifetime increased with increasing frequency. In addition, the unipolar AC TDDB improvement shows a power law dependence on the duty ratio due to a very significant charge trap/detrap effect. This is further validated through a physics-based simulation. On the other hand, bipolar AC stress caused the ion diffusion to be accompanied by the backflow Cu ion drift, thus extending the defect growth rate and improving the TDDB performance. However, no significant frequency and duty ratio dependence on the bipolar AC to DC ratio was found because the critical Cu ion concentration was constrained by the ion diffusion mechanism. This study suggests that actual circuit operation in the AC condition should have a much longer back-end TDDB lifetime than the projection by DC stress assessment for BEOL ELK dielectrics.

12:00 PM
31.8 Sustainable Electronics for Nano-Spacecraft in Deep Space Missions, D.-I. Moon, J.-Y. Park*, J.-W. Han, G.-J. Jeon*, J.-Y. Kim*, J. Moon*, M.-L. Seol, C. K. Kim*, H. C. Lee*, M. Meyyappan and Y.-K. Choi*, NASA Ames Research Center, *KAIST

On-the-fly self-healing devices are experimentally demonstrated for sustainable space electronics. High temperature generated by Joule heating in gate electrode provides on-chip annealing of ionizing radiation, hot carrier, and tunneling damages. With self-healing process, highly scaled SiNW GAA FETs show long-term reliability in Logic, floating body DRAM, and Flash memory. Thermally isolated gate structure is proposed to enhance self-healing effects.