Session 3: Focus Session - Process and Manufacturing Technology 3D Integration and Packaging

Monday, December 4
Grand Ballroom B
Co-Chairs: Kuan-Neng Chen, National Chiao Tung University
Lucile Arnaud, CEA-Leti

1:35 PM
3.1 3D Sequential Integration: Application-driven technological achievements and guidelines (Invited), P. Batude, L. Brunet, C. Fenouillet-Beranger, F. Andrieu, J-P. Colinge, D. Lattard, E. Vianello, S. Thuries, O. Billoint, P. Vivet, C. Santos, B. Mathieu, B. Sklenard, C.-M. V. Lu, J. Micout, F. Deprat, E. Avelar Mercado, F. Ponthenier, N. Rambal, M.-P. Samson**, M. Cassé, S. Hentz, J. Arcamone, G. Sicard, L. Hutin, L. Pasini, A. Ayres, O. Rozeau, R. Berthelon, F. Nemouchi, P. Rodriguez, J-B. Pin*, D. Larmagnac*, A. Duboust*, V. Ripoche*, S. Barraud, N . Allouti, S. Barnola, C. Vizioz, J.-M. Hartmann, S. Kerdiles, P. Acosta Alba, S. Beaurepaire, V. Beugin, F. Fournel, P. Besson**, V. Loup, R. Gassilloud, F. Martin, X. Garros, F. Mazen, B. Previtali, C.Euvrard-Colnat, V. Balan, C. Comboroure, M. Zussy, Mazzocchi, O. Faynot, and M. Vinet, .CEA- leti, Minatec, *Applied Materials, **STMicroelectronics

3D Sequential Integration (3DSI) with ultra-small 3D contact pitch (<100nm) offers new 3D partitioning options at fine granularities. This paper reviews potential applications ranging from computing to sensor interface and gives an update on 3DSI device development. Low-temperature processing techniques have made great progress and High Performance (HP) digital stacked FETs for computing application can be achieved with a 500°C Thermal Budget (TB). In addition, ULK/metal lines capable of withstanding this TB can be used between stacked tiers. Ultra-Low TB FETs (<400°C) have potential for low-power applications and allow for the stacking of multiple layers.

2:00 PM
3.2 Pixel/DRAM/logic 3-layer stacked CMOS image sensor technology (Invited), H. Tsugawa, H. Takahashi, R. Nakamura, T. Umebayashi, T. Ogita, H. Okano, K. Iwase, H. Kawashima, T. Yamasaki*, D. Yoneyama*, J. Hashizume, T. Nakajima, K. Murata, Y. Kanaishi, K. Ikeda*, K. Tatani, T. Nagano, H. Nakayama*, T. Haruta and T. Nomoto, Sony Semiconductor Solutions Corp., Kanagawa, *Sony Semiconductor Manufacturing Corp.

We developed a CMOS image sensor (CIS) chip, which is stacked pixel/DRAM/logic. In this CIS chip, three Si substrates are bonded together, and each substrate is electrically connected by two-stacked through-silica vias (TSVs) through the CIS or dynamic random access memory (DRAM). We obtained low resistance, low leakage current, and high reliability characteristics of these TSVs. Connecting metal with TSVs through DRAM can be used as low resistance wiring for a power supply. The Si substrate of the DRAM can be thinned to 3 μm, and its memory retention and operation characteristics are sufficient for specifications after thinning. With this stacked CIS chip, it is possible to achieve less rolling shutter distortion and produce super slow motion video.

2:25 PM
3.3 Power Inside – Applications and Technologies for Integrated Power in Microelectronics (Invited), C. Ó Mathúna, S. Kulkarni, Z. Pavlovic, D. Casey, J. Rohan, A-M Kelleher, G. Maxwell, J. O’Brien, P. McCloskey, Tyndall National Institute, University College Cork

The emergence of miniaturized and integrated Power Supply on Chip (PwrSoC) and Power Supply in Package (PwrSiP) platforms will be enabled by the application of thin-film, integrated magnetics on silicon. A process flow for, and the design of, a thin-film coupled-inductor, switching at 60MHz, is described. Based on the large signal characterization data, measured up to 100MHz,, the efficiency of the inductor is measured to be 91.7% for a power of 0.5W.

2:50 PM
3.4 3D System Package Architecture as Alternative to 3D Stacking of ICs with TSV at System Level (Invited), R. Tummala, Georgia Tech.

The 3D packaging started in 1970s for packaging of memory packages. Memory density has always been the bottleneck in high performance computing systems that led to two paths; increasing memory density within a chip in 2D and increasing by stacking many either packaged or bare chips in 3D. The barrier to systems performance, however, has been latency and bandwidth between logic and memory. 3D stacking of logic and memory has been viewed as the ultimate solution for a decade but it has its own barriers. While these barrier are being overcome by many approaches, the ultimate goal is to form miniaturized systems with highest performance and reliability at lowest cost. This paper presents a 3D system package architecture to address both bandwidth and other system requirements at system level in contrast to 3D ICs at device level.

3:15 PM Coffee Break

3:40 PM
3.5 Advanced Packaging Saves the Day! – How TSV Technology Will Enable Continued Scaling (Invited), L. England and I. Arsovski, GLOBALFOUNDRIES

Technology scaling is becoming more difficult and costly with each generation. As we scale below 7nm, there is uncertainty in the methodology that will be used for device formation and integration. Now, more than ever, the use of advanced packaging technologies is needed to help extend the lifetimes of our most advanced fab technologies. In this “More Than Moore” era, transistor density can be considered in terms of volume rather than area, and the proliferation of TSV integration is the key enabling technology.

4:05 PM
3.6 Advanced Packaging with Greater Simplicity (Invited), D. C.H. Yu, Taiwan Semiconductor Manufacturing Company

Integrated Fan-Out (InFO) is developed with greater simplicity, based on subtraction in structure, process flow and supply chain management. It achieved un-precedent results compared to others using “additional” structure, including electrical performance, power consumption, thermal resistance, form factor/thickness and cost effectiveness. Greater simplicity continues play critical role for advanced packaging to achieve system PPAC goals.

4:30 PM
3.7 Towards Cube-Sized Compute Nodes: Advanced Packaging Concepts enabling Extreme 3D Integration (Invited), T. Brunschwiler, G. Schlottig, A. Sridhar, P. Bezerra*, P. Ruch, N. Ebejer, H. Oppermann**, J. Kleff**, W. Steller***, M. Jatlaoui^, F. Voiron^, Z. Pavlovic^^, P. McCloskey^^, D. Bremner^^^, P. Parida#, F. Krismer2, J. Kolar2, and B. Michel1, IBM Research – Zurich, *ETH – PES, Zurich, **FhG – IZM, ***FhG – IZM – ASSID, ^Murata, ^^Tyndall National Institute, Cork, ^^^Optocap, Livingston, #IBM TJ Watson Research Center

Novel heat removal and power delivery topologies are required to enable ‘extreme 3D integration’ with cube-sized compute nodes. Therefore, a technology roadmap is presented supporting memory-on-logic and logic-on-logic in the medium and long-term, by (i) dual-side cooling and integrated voltage regulators, and (ii) interlayer cooling and electrochemical power delivery.