Session 3: Compound Semiconductor and High Speed Devices Compound Semiconductors for High Speed RF and Low Power Logic Applications

Monday, December 5, 1:30 p.m.
Continental Ballroom 1-3
Co-Chairs: Lukas Czornomaz, IBM
Han Wui Then, Intel

1:35 PM
3.1 SiGe HBT with fT/fmax of 505 GHz/720 GHz, B. Heinemann, H. Rücker, R. Barth, F. Bärwolf, J. Drews, G. Fischer, A. Fox, O. Fursenko, T. Grabolla, F. Herzel, J. Katzer, J. Korn, A. Krüger, P. Kulse, T. Lenke, M. Lisker, S. Marschmeyer, A. Scheit, D. Schmidt, J. Schmidt, A. Schubert, A. Trusch, C. Wipf, D. Wolansky, IHP

SiGe HBTs featuring fT/fmax/BVCEO = 505 GHz/720 GHz/1.6 V and a minimum CML ring oscillator gate delay of 1.34 ps are presented. The improved speed originates from an optimized vertical profile, the combined application of millisecond annealing and a backend with low thermal budget, as well as lateral device scaling.

2:00 PM
3.2 InGaAs Tri-gate MOSFETs with Record On-Current, C. Zota, F. Lindelow, L.-E. Wernersson, and E. Lind, Lund University

We demonstrate InGaAs tri-gate MOSFETs with an on- current of ION = 650 µA/µm at VDD = 0.5 V and IOFF = 100 nA/µm, enabled by an inverse subthreshold slope of SS = 66 mV/decade and transconductance of gm = 3 mS/µm, a Q-factor of 45. This is the highest reported ION for both Si-based and III-V MOSFETs. These results continue to push III-V MOSFET experimental performance towards its theoretical limit. We find an improvement in SS from 81 to 75 mV/dec. as the effective oxide thickness (EOT) is scaled down from 1.4 to 1 nm, as well as improvements in SS, gd and DIBL from reducing the nanowire width. We also find that electron mobility remains constant as the width is scaled to 18 nm.

2:25 PM
3.3 High Frequency GaN HEMTs for RF MMIC Applications (Invited), M. Micovic, D. Brown, D. Regan, J.Wong, F. Herrault, Y. Tang, D. Santos, S. Burnham, J. Tai, E. Prophet, I. Khalaf, C. McGuire, H. Bracamontes, H. Fung, A. Kurdoghlian, A. Schmitz, HRL Laboratories LLC

We provide an overview of key challenges and technical breakthroughs that led to development of highly scaled GaN HEMT’s having ft > 400 GHz and fmax > 550 GHz and the corresponding IC process. These highly scaled GaN devices have 5 times higher breakdown voltage than transistors with similar high frequency RF power gain in other semiconductor systems (Si, SiGe, InP, GaAs). We also report performance of the first generation of MMIC power amplifiers (PAs) that utilize these highly scaled devices. The power added efficiency (PAE) of 59% measured at a frequency of 32 GHz, bias of 3 V and output power of 24.3 dBm of the first generation Ka-band MMIC PAs that were built using these highly scaled GaN devices, represent a significant improvement in PAE over values reported for other semiconductor technologies at this frequency band as well as for Ka-band MMICs built in lower frequency GaN nodes. Presented data suggest that highly scaled GaN transistors are excellent candidates for MMIC PAs for next generation 28 GHz, 39 GHz, and higher frequency 5G mobile bands, because they would greatly extend battery lifetime in mobile handsets, due to their superior PAE compared to competing semiconductor technologies.

2:50 PM
3.4 Electric-Field Induced F- Migration in Self-Aligned InGaAs MOSFETs and Mitigation, X. Cai, J. Lin, D. Antoniadis, and J. del Alamo, Massachusetts institute of Technology

We have identified and studied a new instability mechanism in self-aligned InGaAs MOSFETs due to F- migration and passivation/depassivation of Si dopants in n-InAlAs cap layer. We successfully eliminate this instability by eliminating n-InAlAs from the device structure. The new device design achieves improved stability and record device performance.

3:15 PM
3.5 W-Band N-Polar GaN MISHEMTs with High Power and Record 27.8% Efficiency at 94 GHz, B. Romanczyk, M. Guidry, S. Wienecke, H. Li, E. Ahmadi, X. Zheng, S. Keller, and U. Mishra, University of California Santa Barbara

The W-band power performance of N-polar GaN MISHEMTs fabricated using a novel device design to mitigate dispersion is presented. A record power-added efficiency of 27.8% is achieved while maintaining an excellent associated output power density of 3.0 W/mm and peak gain of 7.4 dB at 94 GHz.

3:40 PM
3.6 Monolithic Integration of Multiple III-V Semiconductors on Si for MOSFETs and TFETs (Invited), H. Schmid, D. Cutaia, J. Gooth, S. Wirths, N. Bologna*, K. Moselund, and H. Riel, IBM Research – Zurich, *EMPA, Electron Microscopy Center

In this paper we report on our work on the monolithic integration of various III-V compounds on Si using template-assisted selective epitaxy (TASE) and its application for electronic devices. Nanowires, crossbar nanostructures, and micron-sized sheets are epitaxially grown on Si via metal-organic chemical vapor deposition and form the basis for III-V MOSFETs and Tunnel FETs. Epitaxy conditions specific to TASE are discussed and material quality assessed. Here, we focus on InAs and GaSb as a potential all-III-V alternative to complementary group IV technology. Scaled n-FETs as well as both n- and p-channel TFETs are fabricated on Si and illustrate the potential of TASE.

4:05 PM
3.7 Study of RF-Circuit Linearity Performance of GaN HEMT Technology using the MVSG Compact Device Model, U. Radhakrishna, P. Choi, J. Grajal, L.-S. Peh, T. Palacios, and D. Antoniadis, Massachusetts Institute of Technology

This study is a first demonstration of the use of a physical compact model as a tool to identify technology bottlenecks to the linearity performance of emerging devices such as GaN HEMTs and to provide solutions to improve linearity both through device-design and circuit-design techniques. This work investigates the linearity performance of the emergent GaN-HEMT technology targeted for RF-applications, by making use of a physics-based GaN HEMT compact model: MIT Virtual Source GaNFET (MVSG) model to identify the various causes for device-non-linearity and their impact on circuit linearity performance. The model is calibrated and verified against a complete suite of device- measurements in order to identify the impact of device-technology parameters on the non-linear device-behavior as a function of operating class. Well-known non-ideal effects prevalent in GaN technology such as charge-trapping, access-region behavior, and thermal effects are calibrated and the model is used to evaluate the extent of non- linearity (so called ‘soft-compression’) contributed by each of them. Designed using the model, circuit-level linearity improvement techniques such as ‘gm-compensation’ demonstrate improvements in linearity (lower harmonic content and IMD) in medium power-levels with fabricated power amplifiers (PAs).