IEDM

Session 28: Memory Technology In-memory Computing

Wednesday, December 6
Grand Ballroom A
Co-Chairs: Ming Liu, Institute of Microelectronics, CAS
Daniele Ielmini, Politecnico di Milano

9:05 AM
28.1 Modeling-based design of brain-inspired spiking neural networks with RRAM learning synapses, G. Pedretti, S. Bianchi, V. Milo, A. Calderoni*, N. Ramaswamy*, and D. Ielmini, Politecnico di Milano, *Micron Technology

Brain-inspired computing is currently gaining momentum as a viable technology for artificial intelligence enabling recognition, language processing and online unsupervised learning. Brain-inspired circuit design is currently hindered by 2 fundamental limits: (i) understanding the event-driven spike processing in the human brain, and (ii) developing predictive models to design and optimize cognitive circuits. Here we present a comprehensive model for spiking neural networks based on spike-timing dependent plasticity (STDP) in resistive switching memory (RRAM) synapses. Both a Monte Carlo (MC) model and an analytical model are presented to describe experimental data from a state-of- the-art neuromorphic hardware. The model can predict the learning efficiency and time as a function of the input noise and pattern size, thus paving the way for model-based design of cognitive brain-like circuits.

9:30 AM
28.2 A 16Mb Dual-Mode ReRAM Macro with Sub-14ns Computing-In-Memory and Memory Functions Enabled by Self-Write Termination Scheme, W.-H. Chen, W.-J. Lin, L.-Y. Lai, S. Li*, C.-H. Hsu**, H.-T. Lin, H.-Y. Lee**, J.-W. Su**, Y. Xie*, S.-S. Sheu**, and M.-F. Chang, National Tsing Hua University, *UC Santa Barbara, **ITRI

Recent ReRAM devices enable the development of computing-in-memory (CIM) for beyond von Neumann structure. However, wide distribution in ReRAM resistance (R) causes low yield for CIM operations. This work proposes a dual-mode computing (DMc) ReRAM macro structure with a dual- function voltage-mode self-write termination (DV- SWT) scheme to achieve both memory and fundamental CIM functions (AND, OR and XOR operations) with high yield. The DV-SWT increases the read margin for CIM operations by suppressing the R-variations caused by macro-level IR-drop and process variations. A 16Mb DMc-ReRAM full-function macro was fabricated using 1T1R HfO ReRAM devices and 0.15um CMOS process. The measured delay of the CIM operations is less than 14ns, which is 86+x faster than previous ReRAM-based CIM works. This work also represents the first CIM ReRAM macro with ReRAM device and CIM-peripheral circuits fully integrated on the same die.

9:55 AM
28.3 Compressed Sensing Recovery using Computational Memory, M. Le Gallo, A. Sebastian, G. Cherubini, H. Giefers, and E. Eleftheriou, IBM Research-Zurich

Computational memory (CM) is a promising non-von Neumann approach where certain computational tasks are performed within resistive memory units by exploiting their physical attributes. We propose a new method for fast and robust compressed sensing (CS) recovery of sparse signals using CM. For a signal of size N, this method achieves a potential O(N)-fold complexity reduction compared with a standard software approach. Large-scale experimental demonstrations using more than 256k phase-change memory (PCM) devices are presented along with an in-depth device analysis and array-level considerations.

10:20 AM
28.4 Data-Aware NAND Flash Memory for Intelligent Computing with Deep Neural Network (Invited), K. Takeuchi, Chuo University

This paper presents data-aware NAND flash memories. By recognizing the data value, sophisticated data management such as storing important data in reliable memory cells or adaptively optimizing read voltage are realized. Consequently, intelligent computing such as image recognition with deep neural network, data compression and disaggregated hybrid storage are achieved.

10:45 AM
28.5 Reconfigurable NAND/NOR logic gates in 28 nm HKMG and 22 nm FD-SOI FeFET technology, E. T. Breyer, H. Mulaosmanovic,; T. Mikolajick, and S. Slesazeck, NaMLab gGmbH

We present for the first time a reconfigurable NAND/NOR logic gate based on a single ferroelectric FET (FeFET), having hafnium oxide as the ferroelectric material and a pull-up device connected in series. Electrical results and SPICE simulations reveal the feasibility of the concept for 28nm HKMG and 22nm FD-SOI FeFET technology.