IEDM

Session 23: Nano Device Technology Negative Capacitance and Other Steep-Slope Devices 2

Tuesday, December 5
Continental Ballroom 6
Co-Chairs: Deji Akinwande, University of Texas – Austin
Bill Taylor, GLOBALFOUNDRIES

2:05 PM
23.1 Negative Capacitance Enables FinFET and FDSOI Scaling to 2 nm Node, V. Pi-Ho Hu, P.-C. Chiu, A.B. Sachid*, and C. Hu*, National Central University, *University of California, Berkeley

The scaling potential of negative capacitance FinFET and FDSOI (NC-FinFET and NC-FDSOI) are studied for technology nodes down to 2nm. According to ITRS 2.0, FinFET scaling ends at 6/5nm node due to the scaling limits of fin width (6 nm Wfin) and FDSOI scaling ends at 11/10 nm due to scaling limit of the channel thickness (3 nm Tch). We present TCAD simulation evidence that using these Wfin and Tch, and negative capacitance enables FinFET and FDSOI scaling to 2 nm node. NC-FinFET and NC-FDSOI at 2 nm node show Ioff < 100nA/um and 10%~29% higher Ion compared with 2nm FinFET(97uA/um Ioff) and FDSOI(46uA/um Ioff). NC-FDSOI exhibits similarly strong back-gate bias effects on Ioff and Ion compared with FDSOI.

2:30 PM
23.2 Energy-Efficient HfAlOx NCFET: Using Gate Strain and Defect Passivation to Realize Nearly Hysteresis-Free Sub-25mV/dec Switch with Ultralow Leakage, C.-C.Fan, C.-H. Cheng*, Y.-R. Chen, C. Liu*, and C.-Y. Chang, National Chiao-Tung University, *National Taiwan Normal University

HfAlOx NCFETs achieve the 8 orders-of-magnitude current ratio. HfAlOx NCFETs with gate strain exhibits 66% Ion enhancement and 27% Vt reduction. The additional defect passivation can mitigate interface depolarization field and help to reinforce surface potential amplification effect.

2:55 PM
23.3 Ferroelectric Al:HfO2 Negative Capacitance FETs, H. Lee, P.-G. Chen, S.-T. Fan, Y.-C. Chou, C.-Y. Kuo, C.-H. Tang, H.-H. Chen, S.-S. Gu, R.-C. Hong, Z.-Y. Wang, S.-Y. Chen, C.-Y. Liao, K.-T. Chen*, S. T. Chang*, M.-H. Liao, K.-S. Li**, and C. W. Liu, National Taiwan University, *National Chung Hsing University, **National Nano Device Laboratories

The first experimental demonstration of ferroelectric Al:HfO2 (FE- HAO) FETs is proceeded with negative capacitance (NC) effect. The SS of 40 mV/dec and 39 mV/dec for forward and reverse sweep, respectively, as well as almost hysteresis-free are achieved. The partial orthorhombic phase of FE-HAO is confirmed both with (PMA) and without (PDA) a capping layer. A gradual transition of polarization after 1000°C annealing is obtained with increasing Al concentration for large remanent polarization (Pr), coercive field (Ec), and high dielectric constant. The similar physical thickness (~7nm) of ferroelectric-HfZrOx (FE-HZO) FET is discussed for comparison. The transient behavior is performed at room temperature and low temperature, and the dynamical NC model is discussed.

3:15 PM Coffee Break

3:40 PM
23.4 Physics and Technology of Electronic Insulator-to-Metal Transition (E-IMT) for High On/Off Ratio and Low Voltage in Device Applications, J. Lin, K. Alam, L. Ocola, Z. Zhang*, S. Data**, S. Ramanathan*, S. Guha, Argonne National Laboratory, *Purdue University, **University of Notre Dame

New device concepts related to both computing and biological function emulation are emerging rapidly based upon the electronic insulator-to-metal transition (E-IMT) effect that some oxides, such as VO2, exhibit. However, the experimental E-IMT devices to-date are limited to an ON/OFF ratio of ~102, resulting in a small and inadequate dynamic range in device operation. In addition, the voltage that drives the E-IMT is high, typically above 1 V. In this paper, we investigate the physics and technology toward realizing both high ON/OFF and low-voltage E-IMT devices. We show that, the ON/OFF ratio, critical E-IMT voltage, and device reliability are closely coupled. A predictive model is developed and shows that, for reliable operation, the maximum ON/OFF ratio of an E-IMT device should follow a square-root relation with the strength of the thermally driven insulator-to-metal transition (T-IMT). This new design rule is verified by systematic experiments using prototypical VO2 E-IMT devices. Through this study, we achieve a record value of reliable E-IMT with an ON/OFF ratio of 3.5×103 at 1.2 V –greater than 10x improvement over the previous state-of-the-art. A record low voltage of IMT switching at 0.3 V (ON/OFF ratio =20) is also demonstrated. The proposed universal design rule is widely applicable for a range of emerging applications based on E-IMT devices. As an experimental example, the E-IMT based transistors show an ultra-steep subthreshold swing (<1mV/dec) and ON/OFF ratio >103.

4:05 PM
23.5 Sub-60 mV/dec Ferroelectric HZO MoS2 Negative Capacitance Field-effect Transistor with Internal Metal Gate: the Role of Parasitic Capacitance, M. Si, C. Jiang, C.-J. Su*, Y.-T. Tang*, L. Yang, W. Chung, M. A. Alam and P. D. Ye, Purdue University, *National Nano Device Laboratories,

Steep-slope MoS2 NC-FETs with ferroelectric HZO and IMG are demonstrated. SS less than 50 mV/dec is obtained for both forward and reverse gate voltage sweeps, with minimum SSFor=37.6 mV/dec and SSRev=42.2 mV/dec. The impact of parasitic capacitance on SS and dynamic hysteresis is systematically studied by both experiment and simulation.

4:30 PM
23.6 Negative Capacitance 2D MoS2 Transistors with Sub-60mV/dec Subthreshold Swing over 6 Orders, 250 μA/μm current density, and Nearly-Hysteresis-Free, Z. Yu, H. Wang, W. Li, S. Xu, X. Song*, S. Wang, P. Wang, Peng Zhou*, Y. Shi, Y. Chai** and Xinran Wang, Nanjing University, Fudan University, *The Hong Kong **Polytechnic University

A high-performance and low-power MoS2 NCFET is demonstrated in this work, with ultra-low subthreshold swing (SS) of 23 mV/dec, sub-60 mV/dec over 6 orders of ID, nearly hysteresis-free, small |Vth|

4:55 PM
23.7 NbO2 based threshold switch device with high operating temperature (>85°C) for steep-slope MOSFET (~2mV/dec) with ultra-low voltage operation and improved delay time, J. Park, D. Lee, J.M. Yoo and H. Hwang, Pohang University of Science and Technology

To realize a steep slope field-effect transistor (FET) with low leakage current and controllable operating bias, NbO2 threshold switching (TS) device is connected in series with the gate side of a MOSFET. Thanks to the TS device showing abrupt transition between the OFF and ON states at threshold voltage (Vth), the implemented transistor exhibits extremely low leakage current (10-7μA/ μm), high ION/IOFF ratio (>106), sub-2 mV/dec subthreshold swing, drift-free characteristic and high temperature operation (>85°C). Furthermore, since the Vth is tunable by controlling thickness of the NbO2 TS device, the new NbO2-MOSFET can fulfill various demands of operating bias conditions. In addition, we confirmed through a simulation that the CMOS inverter with NbO2 connected to the gate side showed fast inverting speed of over 300 MHz at ultra-low voltage (200mV).