Session 22: Process and Manufacturing Technology Advanced Metal Gate and Contact Technology
Tuesday, December 5
Continental Ballroom 5
Co-Chairs: Qi Xie, ASM
Guilhem Larrieu, LAAS CNRS
22.1 High-k Metal Gate Fundamental Learning and Multi-VT Options for Stacked Nanosheet Gate-All-Around Transistor, J. Zhang, T. Ando, C. W. Yeung, M. Wang, O. Kwon*, R. Galatage**, R. Chao, N. Loubet, B. K. Moon**, R. Bao, Reinaldo A. Vega, J. Li, C. Zhang, Z. Liu, M. Kang*, X. Miao1, J. Wang, S. Kanakasabapathy, V. S Basker, H. Jagannathan, T. Yamashita1, IBM, *SAMSUNG ELECTRONICS, **GLOBALFOUNDRIES
In this paper, we report multi-threshold-voltage (multi-VT) options for stacked Nanosheet gate-all-around (GAA) transistors. VT can be modulated through workfunction metal (WFM) thickness as well as the inter-nanosheet spacing (Tsus), the combination of which may be leveraged to increase the number of undoped VT offerings within a CMOS device menu relative to a FinFET CMOS device menu, which fundamentally does not have Tsus as a VT tuning option. Hence we propose our multi-VT scheme by taking advantage of the unique structure of stacked GAA transistor.
22.2 Highly Conductive Metal Gate Fill Integration Solution for Extremely Scaled RMG Stack for 5 nm & Beyond, N. Yoshida, S. Hassan, W. Tang, Y. Yang, W. Zhang, S. C. Chen, L. Dong, H. Zhou, M. Jin, M. Okazaki, J. Park, N. Bekiaris, R. Hung, J. Zhou, Y. Lei, P. Ma, X. Tang, T. Miyashita, N. Kim and E. Yieh, Applied Materials Inc.
This paper describes replacement-metal-gate fill integration solutions with a cobalt-reflow process combined with a thin barrier layer for future node FinFET and gate-all-around technology. A unique Co-fill process combined with scaled barrier thickness is proposed as a new RMG solution for gate conductance extendibility and VT control.
22.3 Integrated Dual SPE Processes with Low Contact Resistivity for Future CMOS Technologies, Heng Wu, S.-C. Seo, C. Niu*, W. Wang, G. Tsutsui, O. Gluschenkov, Z. Liu, A. Petrescu, A. Carr, S. Choi, S. Tsai*, C. Park*, I. Seshadri, A. Desilva, A. Arceo, G. Yang*, M. Sankarapandian, C. Prindle*, K. Akarvardar*, C. Durfee*, J. Yang, P. Adusumilli, B. Miao, J. Strane, W. Kleemeier*, M. Raymond*, K. Choi, F.-l. Lie, T. Yamashita, A. Knorr*, D. Gupta, D. Guo, R. Divakaruni, H. Bu, and M. Khare, IBM Semiconductor Technology Research, *GLOBALFOUNDRIES Inc
In this study, a manufacturable CMOS dual solid phase epitaxy (SPE) process with Rhocc < 2.2×10-9 ohm*cm2 on both NFET and PFET is demonstrated on the hardware with 7nm ground rule. Contact resistivity reduction strategies of both the conventional approach of high in-situ doped epi and the novel SPE processes are systematically studied on device and ring oscillator (RO) level. Clear improvement in the RO delay is accomplished by the novel dual SPE process on the CMOS flow. Stronger performance benefit is demonstrated with smaller contact sizes towards future CMOS technology nodes.
3:15 PM Coffee Break
22.4 Comprehensive study of Ga Activation in Si, SiGe and Ge with 5 × 10-10 Ω cm2 Contact Resistivity Achieved on Ga doped Ge using Nanosecond Laser Activation, L. Date**, J. del Agua Borniquel**, K. Hollar**, F. A. Khaja**, W. Aderhold**, A. J. Mayur**, J.Y. Lee**, H. van Meer**, D. Mocuta, N. Horiguchi, N. Collaert, K. De Meyer, Y.-L. Jiang*, Imec, *Fudan University, **Applied Materials
Ga activation in Si, SiGe and Ge are studied comprehensively. A low Ti/p-Ge contact resistivity of 1.2×10-9 ohmic·cm2 is approached using Ga doping and low temperature activation, while a record-low contact resistivity for p-Ge down to 5×10-10 ohmic·cm2 with high activation level of 5×1020cm-3 is achieved using nanosecond laser activation.
22.5 Cluster-Preforming-Deposited Amorphous WSin (n = 12) Insertion Film of Low SBH and High Diffusion Barrier for Direct Cu Contact, N. Okada, N. Uchida, S. Ogawa, K. Endo, T. Kanayama, National Institute of Advanced Industrial Science and Technology (AIST)
The insertion of WSi12 films reduces the SBH to 0.32 eV at W/n-Si and to 0.51 eV at W/Ge/p-Si junctions, and extends a TDDB lifetime > 10 years at 100ºC under 5 MV/cm stress for Cu MOS capacitors, thus enabling the direct Cu contact at S/D in advanced CMOS.