Session 21: Characterization, Reliability and Yield Reliability and Characterization of Memory Devices, Contacts and Interfaces

Tuesday, December 6, 2:15 p.m.
Imperial Ballroom A
Co-Chairs: Seokiu Lee, SK Hynix
Ehrenfried Zschech, Fraunhofer IKTS Dresden

2:20 PM
21.1 Reliability Study of a 128Mb Phase Change Memory Chip Implemented with Doped Ga-Sb-Ge with Extraordinary Thermal Stability, W.-C. Chien, H.Y. Cheng, M. BrightSky*, A. Ray*, C.W. Yeh, W. Kim*, R. Bruce*, Y. Zhu*, H.Y. Ho, H.L. Lung and C. Lam, Macronix, *IBM T.J. Watson Research Center

The comprehensive reliability study for the relationship between cycling endurance and thermal stability on a 128Mb PCM chip using modified doped Ga-Sb-Ge material is demonstrated. The chip exhibited excellent data retention for 10 years at 215C after 1K pre-cycles, 210C after 10K pre-cycles, and 205C after 100K pre-cycles.

2:45 PM
21.2 Impact of the Filament Morphology on the Retention Characteristics of Cu/Al2O3-based CBRAM Devices, K. Ota, A. Belmonte*, Z. Chen*, A. Redolfi*, L. Goux* and G. S. Kar*, Toshiba Corp., *imec

In this paper, we demonstrate that the morphology of the conductive filament is the key parameter to control the data retention characteristics of CBRAM devices. In particular, we prove that the evolution of the LRS and HRS distributions is qualitatively related to the filament shape, whereas it is influenced quantitatively by the materials constituting the CBRAM stack, and we propose the peculiar hourglass filament shape as a solution for enabling optimal retention performances. Further analysis of the effect of cycling on retention confirms the key role of the filament morphology in the CBRAM data retention trend.

3:10 PM
21.3 Microsecond Transient Thermal Behavior of HfOx-based Resistive Random Access Memory Using a Micro Thermal Stage (MTS), Z. Jiang, Z. Wang, X. Zheng, S. Fong, S. Qin, H.-Y. Chen*, C. Ahn, J. Cao, Y. Nishi and H. -S. P. Wong, Stanford University, *GigaDevice Semiconductor, Inc.

Microsecond transient thermal disturbance (TD) on the conduction and switching of HfOX-based resistive random access memory (RRAM) is investigated using a micro thermal stage (MTS). Temperature-dependent measurement (298 – 1134 K) induced from MTS is applied to the RRAM during forming, read, write, and reliability measurements for DC and AC conditions.In this work, the time scale of the temperature- dependent measurement is extended from DC down to ~ 10 μs. Various mechanisms (drift, Soret and Fick diffusion) of the ion migration are analyzed using MTS-induced heating. A compact model is developed to capture drift and diffusion mechanisms. TD in the middle layer of 3D array (64 × 64 × 32) is estimated. More than 20 % devices can be programmed with a resistance shift at the next cycle caused by TD. 2.2 % devices may have a write failure.

3:35 PM
21.4 Identify the Critical Regions and Switching/failure Mechanisms in non-filamentary RRAM (a-VMCO) by RTN and CVS Techniques for Memory Window Improvement, J. Ma, Z. Chai, W. Zhang, B. Govoreanu*, J. Zhang, Z. Ji, B. Benbakhti, G. Groeseneken* and M. Jurczak*, Liverpool John Moores Univeristy, *imec

A novel method combining RTN, CVS and Weibull-plot has been developed for non-filamentary RRAM, which, for the first time, enables the identification of its switching and failure mechanisms at defect level, through directly observing the profile modulation of pre-existing defects and progressive formation of conductive percolation path by generated defects.

4:00 PM
21.5 Technology for Reliable Spin-Torque MRAM Products (Invited), J.M. Slaughter, K. Nagel, R. Whig, S. Deshpande, S. Aggarwal, M. DeHerrera, J. Janesky, M. Lin, H.-J. Chia, M. Hossain, S. Ikegawa, F.B. Mancoff, G. Shimon, J.J. Sun, M. Tran, T. Andre, S. M. Alam, F. Poh*, J.H. Lee*, Y.T. Chow*, Y. Jiang*, H.X. Liu*, C.C. Wang*, S.M. Noh*, T. Tahmasebi*, S.K. Ye* and D. Shum*, Everspin Technologies, Inc., *GLOBALFOUNDRIES

In this paper we present an overview of important features for reliable and manufacturable ST-MRAM as well as new results in two areas: pMTJ arrays with data retention sufficient for programming before 260°C wave solder, and performance of a 256Mb, DDR3 ST-MRAM product chip

4:25 PM
21.6 Understanding Cycling Endurance in Perpendicular Spin-transfer Torque (p-STT) Magnetic Memory, R. Carboni*, S. Ambrogio*, W. Chen, M. Siddik, J. Harms, A. Lyle, W. Kula, G. Sandhu and D. Ielmini*, Micron Technology, *Politecnico di Milano

Perpendicular spin-transfer torque (p-STT) memory is attracting an increasing interest as storage class memory (SCM) or static/dynamic RAM replacement. In these applications, high speed and extended endurance are essential and sometimes conflicting requirements. This work addresses cycling endurance of p-STT devices by pulsed experiments and modeling of the dielectric breakdown. We present a new endurance model able to predict the STT endurance as a function of applied voltage, pulse width, pulse polarity and delay time. The trade-off between write time and endurance for RAM replacement is finally addressed.

4:50 PM
21.7 Graphenic Carbon-Silicon Contacts for Reliability Improvement of Metal-Silicon Junctions, M. Stelzer and F. Kreupl, Technical University of Munich

Graphenic carbon-silicon Schottky contacts are demonstrated that have a very low Schottky barrier height. In contrast to conventional metal-based contacts (like TiSi), they are over 100 million times more stable against high current pulses. The C-Si contact properties even show promise to establish an ultra-low, high temperature stable contact resistance.