Session 21: Characterization, Reliability and Yield Memory Reliability

Tuesday, December 5
Continental Ballroom 1-3
Co-Chairs: Moonyoung Jeong, Samsung
Tanya Nigam, GlobalFloundries

2:05 PM
21.1 Impact of external magnetic field on embedded perpendicular STT-MRAM technology qualified for solder reflow, C.-Y. Wang, M.-C. Shih, Y.-H. Lee, W. Wang, L. Thomas*, Y.-J. Lee*, H. Liu*, J. Zhu*, G. Jan*, A. Wang*, T. Zhong*, P.-K. Wang*, D. Lin, C.-H. Chen, C.-Y. Chang, C.-H. Weng, T.-W. Chiang, K.-H. Shen, W.-J Gallagher, H. Chuang, TSMC, *TDK

External magnetic field resistance under write, read operations for perpendicular STT-MRAM qualified for 260oC solder reflow is comprehensively reported for the first time. We show that the most critical polarization direction is writing from parallel to anti-parallel state with external field opposed to both the final free layer direction and the bottom pinned layer direction. It is also found that free layer failure to switch is the major cause rather than unexpected pinned layer flipping. Furthermore, various key factors including temperature, write condition and MTJ film stack are also studied here. Finally, we demonstrate that a low chip failure rate of 0.001 ppm can be achieved with an ECC scheme for external magnetic fields up to 240 Oe at 85oC.

2:30 PM
21.2 Experimental and theoretical verification of channel conductivity degradation due to grain boundaries and defects in 3D NAND, A. Subirats, A. Arreghini, E. Capogreco, R. Delhougne, C.-L. Tan, A. Hikavyy, L. Breuil, R. Degraeve, V. Putcha, G. Van den bosch, D. Linten and A. Furnémont, IMEC

In this paper, Epi-Si process is used to investigate the impact of traps and grain boundaries in vertical 3D NAND. With this channel morphology, we show that the defects have a reduced impact on device performances compared to the usual poly-Si channel devices. These results are also confirmed and extrapolated to other geometry using 3D TCAD simulations.

2:55 PM
21.3 Impact of Temperature on the Amplitude of RTN Fluctuations in 3-D NAND Flash Cells, G. Nicosia, A.Mannara, D. Resnati, G. M. Paolucci*, P. Tessariol*, A. L. Lacaita, A.S.Spinelli, A. Goda*, and C. Monzio Compagnoni, Politecnico di Milano, *Micron Technology Inc.

We show that the average amplitude of RTN fluctuations in 3-D NAND Flash cells increases when temperature is reduced. This is explained through TCAD simulations in terms of stronger nonuniformities in the polysilicon channel inversion at lower temperatures, increasing the dVT of traps at or close to the polysilicon grain boundaries.

3:15 PM Coffee Break

3:40 PM
21.4 RTN based Oxygen Vacancy Probing Method for Ox-RRAM Reliability Characterization and Its Application in Tail Bits, P. Huang, D. B. Zhu, C. Liu, Z. Zhou, Z. Dong, H. Jiang, W. S. Shen, L. F. Liu, X. Y. Liu*, and J. F. Kang, Peking University & National Key Laboratory of Science and Technology on Micro/Nano Fabrication

Physical mechanism for Random-telegraph-noise (RTN) in oxide based resistive switching memory (Ox-RRAM) is proposed with new insight that the noticeable current fluctuation is attributed to the activation and deactivation of oxygen vacancy (VO) in the filament gap region. Based on the mechanism, RTN based VO probing method is first proposed to analyze properties of each VO and detect the VO count in the filament gap region. The proposed method can establish a connection between the microcosmic VO properties and the Ox-RRAM reliability. Using the proposed VO probing method, we revealed that the tail bits of high resistance state originate from the redundant VO generation in the filament gap region in the ineffective RESET phase. Furthermore, an optimized operation scheme is presented to suppress the tail bits.

4:05 PM
21.5 Fundamental limitations of existing models and future solutions for dielectric reliability and RRAM applications (Invited), E. Wu, A. Kim, T. Ando, R. Muralidhar, B. Li, R. Southwick, P. Jamison, T. Shaw, J. Stathis, and G. Bonilla IBM Research Div.

Two important engines lie at the heart of dielectric reliability assessment and prediction methodologies: a statistical distribution model and a field/voltage accelera-tion model for data parameter extraction and reliability projection. The Weibull/ Poisson model and constant field-acceleration E-model are useful for more-or-less ideal situations, but new applications and experimental findings have challenged and exposed the fundamental limitations of these decades-old models. The time-dependent clustering model and power-law field/voltage models have emerged as promising solutions to meet these new challenges in a wide range of applications from dielectric breakdown (BD) statistics in BEOL/ MOL/FEOL cases to Reset/Set statistics of RRAM opera-tions. Recent advances in atomistic simulation and mi-croscopic modeling provide fresh insights for the correct choice of field/voltage acceleration models.

4:30 PM
21.6 Overcoming the Reliability Limitation in the Ultimately Scaled DRAM Using Silicon Migration Technique by Hydrogen Annealing, S.-W. Ryu, K. Min, J. Shin, H. Kwon, D. Nam, T. Oh, T.-S. Jang, M. Yoo, Y. Kim, S. Hong, SK Hynix Semiconductor Inc.

We demonstrated a highly reliable buried-gate saddle-fin cell-transistor using silicon migration technique of hydrogen annealing after a dry etch to form the saddle-fin structure in a fully integrated 2y-nm 4Gb DRAM. It clearly shows a reduction in interface trap density with highly enhanced variable-retention-time and Row-Hammering immunity.