Session 20: Circuit and Device Interaction Path-Forward for Advanced CMOS Scaling
Tuesday, December 5
Grand Ballroom B
Co-Chairs: Anda Mocuta, imec
Yanfeng Wang, Nvidia
20.1 Overcoming Interconnect Scaling Challenges Using Novel Process and Design Solutions to Improve Both High-Speed and Low-Power Computing Modes, K. Vaidyanathan, D. H. Morris, U. E. Avci, I. S. Bhati, L. Subramanian, J. Gaur, H. Liu,; S. Subramoney, T. Karnik, H. Wang and I. A. Young, Intel Corporation
Interconnect scaling in future CMOS technologies is projected to cause an unprecedented increase in resistance, making interconnects the key performance limiter instead of transistors. We present device-circuit-architecture solutions using reconfiguration of buffered interconnects and execution architecture. Combined, these techniques improve performance by 35% and preserve energy efficiency.
20.2 Impact of Aggressive Fin Width Scaling on FinFET Device Characteristics, X. He, J. Fronheiser, P. Zhao, Z. Hu, S. Uppal, X. Wu, Y. Hu, R. Sporer, L. Qin, R. Krishnan, E. M. Bazizi, R. Carter, K. Tabakman, A. K. Jha, H. Yu, O. Hu, D. Choi, J. G. Lee, S. B. Samavedam, D.K. Sohn, GLOBALFOUNDRIES
Fin width scaling is required to improve FinFET electrostatics for future technology nodes. This paper studies the benefits, trade-offs and limitations of aggressive fin width scaling down to 1.6nm on logic and SRAM device characteristics. AC performance boost opportunity from gate length scaling along with fin width scaling is discussed.
20.3 Design Technology Co-Optimization of 3D-monolithic standard cells and SRAM exploiting dynamic back-bias for ultra-low-voltage operation, F. Andrieu, R. Berthelon, R. Boumchedda, G. Tricaud, L. Brunet, P. Batude, B. Mathieu, E. Avelar, A. Ayres de Sousa, G. Cibrario, O. Rozeau, J. Lacord, O. Billoint, C. Fenouillet-Béranger, S. Guissi**, D. Fried**, P. Morin*, J.P. Noel*, B. Giraud, S. Thuries, F. Arnaud*, M. Vinet, CEA-Leti, *STMicroelectronics, **Coventor
We have fabricated 3D-monolithic transistors on two tiers. We experimentally evidence the asymmetric double-gate (DG) behavior of a top-tier transistor, resulting in a better ON-state current (ION) / OFF-state current (IOFF) tradeoff than in single-gate (SG) mode. Moreover, a 3D-shared contact between a top and bottom electrode was experimentally demonstrated; paving the way for a local back gate, possibly connected with the top gate by a 3D-shared contact. Assuming such a construct, we have performed extensive layout and spice simulations of standard cells and SRAMs. We evidence that the back-gate overlap on the source and drain must be minimized to mitigate the parasitic capacitances. The best layout configurations of a loaded 1-finger inverter yields a 24% frequency gain at a given static power and VDD=0.6V supply voltage, compared to SG, or to a static power divided by 5, 2017 compared to SG under Forward Body Bias (FBB). These performance boosts may be obtained without any area penalty. Similarly, a 29% improvement of the read and write currents of 6T SRAMs is contemplated at VDD=0.8V. Such new functionality provided by 3D-monolithic even enables making 4T SRAMs that are fully functional at VDD=0.8V by improving their retention and, in turn, the maximum number of bitcells per column from 50 (SG) to 300 with a dynamic back-bias.
3:15 PM Coffee Break
20.4 Power Aware FinFET and Lateral Nanosheet FET Targeting for 3nm CMOS Technology, D. Yakimets, M. Garcia Bardon, D. Jang, P. Schuddinck, Y. Sherazi, P. Weckx, K. Miyaguchi, B. Parvais, P. Raghavan, A. Spessot, D. Verkest, and A. Mocuta, imec
We show how 5.5 tracks standard cells can be enabled at gate pitch 42nm and metal pitch 21nm. A device downselection methodology driven by power and performance targets is introduced, demonstrating that three stacked nanosheets are competitive with FinFETs made with two fins while relaxing the constraints on design rules.
20.5 Stacked nanosheet fork architecture for SRAM design and device co-optimization toward 3nm, P. Weckx, J. Ryckaert, V. Putcha, A. De Keersgieter, J. Boemmels, P. Schuddinck, D. Jang, D. Yakimets, M. G. Bardon, L. -Å. Ragnarsson, P. Raghavan, R. R. Kim, A. Spessot, D. Verkest, and A. Mocuta1, imec
This paper discusses SRAM scaling beyond the 5nm technology node and highlights the fundamental scaling limits due to FinFET and Gate all-around (GAA) technology. Therefore, a novel vertically stacked lateral nanosheet architecture using a forked gate structure is proposed showing superior performance and area scaling with limited additional processing complexity.
20.6 A Novel Performance Model for State-of-the-art Processors by Modernization of Rent’s Rule, D. Prasad, S. Sinha*, B. Cline*, S. Moore* and A. Naeemi, Georgia Institute of Technology, *Arm Inc
Faithful a priori estimation of system performance has long been the foundation for early device, circuit, and micro-architectural evaluation. For over two decades, Rent’s power-law has been a popular modelling methodology for predicting interconnect characteristics of a system. However, with dimensional scaling, interconnects have become increasingly important, and the existing models do not provide accurate interconnect estimates; at worst, current Rent’s-based models heavily under-estimate interconnect delay, and power. At the same time, microprocessor designs are also evolving in order to cope with the rapidly changing technology landscape, which together can drastically influence the overall performance characteristics of the designs. For the first time, this paper argues the validity of Rent’s method in the era of rapid technology and, microprocessor-design advancements. A new approach to Rent’s model is proposed which addresses the inability of the current Rent’s approach to accurately capture standard cell level, and design characteristics that are inherent to the way we design microprocessors today. The proposed models are validated against a rich database of state-of-the-art commercial microprocessors at 14/16nm, 10nm and 7nm process nodes, and the results illustrate the importance of design-specific technology prediction.