Session 2: Memory Technology ReRAM and Selectors
Monday, December 4
Grand Ballroom A
Co- Chairs: Rainer Waser, RWTH Aachen University
Gabriele Navarro , CEA-Leti
2.1 Breakthrough of Selector Technology for cross-point 25-nm ReRAM, S. G. Kim, J. C. Lee, T. J. Ha, J. H. Lee, J. Y. Lee, Y. T. Park, K. W. Kim, W. K. Ju, Y. S. Ko, H. M. Hwang, B. M. Lee, J. Y. Moon, W. Y. Park, B. G. Gyun, B.-K. Lee, D. Yim, and S.-J. Hong, SK Hynix Inc.
In this paper, the authors report for the first time the outstanding selector performance from an innovative oxide selector. SiO2, one of conventional and common materials in semiconductor industry, was chosen as a matrix oxide material. Metal atoms which are non-mobile and easy to handle were injected into the oxide films. Off-current and threshold voltage (Vth) could be controlled by using arsenic (As), which doping method and concentration were carefully investigated to achieve threshold switching behavior. Finally ReRAM (Resistance switching Random Access Memory) cell array consisted of one selector-one resistor (1S1R) was successfully demonstrated with the full integration of the newly developed selector.
2.2 An Ultra High Endurance and Thermally Stable Selector based on TeAsGeSiSe Chalcogenides Compatible with BEOL IC Integration for Cross-Point PCM, H. Y. Cheng, W. C. Chien, I. T. Kuo, E. K. Lai, Y. Zhu*, J. L. Jordan-Sweet*, A. Ray*, F. Carta*, F. M. Lee, P. H. Tseng, M. H. Lee, Y. Y. Lin, W. Kim*, R. Bruce*, C. W. Yeh, C. H. Yang, M. BrightSky* and H. L. Lung, Macronix International Co., Ltd., *IBM TJ Watson Research Center
We present the results of a primary study on a OTS chalcogenide material system (TeAsGeSi) that incorporating Se and an extra dopant. Vth and IOFF are trade-off parameters that can be tuned by modification of OTS composition, thickness and process temperature. The resulting new selector material demonstrated excellent endurance (>1010 with 50ns-pulsed 400uA On-current) and robust OTS characteristics after 350 C/30 mins annealing. The thin film could withstand 500 C annealing.
2.3 In-depth investigation of programming and reading operations in RRAM cells integrated with Ovonic Threshold Switching (OTS) selectors, M. Alayan, E. Vianello, G. Navarro, C. Carabasse, S. La Barbera1, A. Verdy, N. Castellani, A. Levisse, G. Molas, L. Grenouillet, T. Magis, F. Aussenac, M. Bernard, B. DeSalvo, J. M. Portal*, E. Nowak, CEA, LETI, *Aix-Marseille Université, IM2NP, CNRS UMR
This paper presents an HfO2 based resistive switching memory (RRAM) in series with a GeSe- based Ovonic Threshold Switching (OTS) selector. Detailed investigation of the main memory operations, forming, set, reset and read is presented for the first time to our knowledge. An innovative reading strategy is proposed. The selector switching is performed only if the RRAM cell is in the Low Resistive State (LRS), while the reading of the High Resistive State (HRS) is performed without switching the OTS selector, preventing disruptive reading when the RRAM cell is in HRS. Up to 106 read cycles have been demonstrated with a stable memory window of one decade and a stable OTS OFF state.
2:50 PM Coffee Break
2.4 BEOL Based RRAM with One Extra-mask for Low Cost, Highly Reliable Embedded Application in 28 nm Node and Beyond, H. Lv, X. Xu, P. Yuan, D. Dong, T. Gong, J. Liu, Z. Yu, P. Huang***, K. Zhang, C. Huo, C. Chen, Y. Xie, Q. Luo, S. Long, Q. Liu, J. Kang***, D. Yang*, S. Yin*, S. Chiu* and M. Liu, Chinese Academy of Sciences, *Semiconductor Manufacturing International Corporation, **University of Chinese Academy of Sciences, ***Peking University
In this work, we demonstrated a low cost, BEOL based embedded RRAM technology by adding only one extra mask on standard 28 nm logic platform. Satisfactory characteristics such as forming free, high on/off ratio (>100) and high operation speed (<100 ns) were achieved. Array level performance on thermal stability shows both LRS and HRS exhibit excellent stability at high temperature up to 260 oC. The resistance fluctuation caused by RTN signal and atomic structural change were clarified experimentally. Memory window and reading voltage selection are crucial to diminish the resistance variation. Compared with conventional eFLASH, this BEOL based RRAM technology provides a competitive solution for low power, low cost embedded application in 28 nm node and beyond.
2.5 A Comprehensive Study of 3-stage High Resistance State Retention Behavior for TMO ReRAMs from Single Cells to a Large Array, Y.-H. Lin, Y.-H. Ho, M.-H. Lee, C.-H. Wang, Y.-Y. Lin, F.-M. Lee, K.-C. Hsu, P.-H. Tseng, D.-Y. Lee, K.-H. Chiang, K.-C. Wang, T.-Y. Tseng*,and C.-Y. Lu, Macronix International Co., Ltd., *National Chiao Tung University
For the first time, the retention of high resistance state in ReRAM is found to compose of three stages — extending tail-bits, distribution shift, and distribution broadening. A three-dimensional kinetic Monte Carlo simulation is proposed to explain the mechanisms and resistance fluctuation of each stage in different time and temperature scales.
2.6 Integrated HfO2-RRAM to Achieve Highly Reliable, Greener, Faster, Cost-Effective, and Scaled Devices, C.H. Ho, S.-C. Chang, C.-Y. Huang, Y.-C. Chuang, S.-F. Lim, M.-H. Hsieh, S.-C. Chang, and H.-H. Liao, Winbond Electronics Corp.,
For the first time, this work demonstrated a 90nm 512Kb SPI HfO2-RRAM product vehicle successfully with reducing read / write power by 18X / 2X, boosting read / write speed by 5X / 10X, and scaling feature size by 2X, compared to presented 512Kb SPI EEPROM; while sustaining high reliability on million cycle endurance, even better post-cycle retention (85oC retention 100years for post 100K cycles), and 150oC high temperature operation, by optimized mismatching, read-integrity, relaxation, and noise as discussed in this work. Technology also offers alternative solution for greener, highly-reliable, and scaled NOR Flash applications. A new plasma dicing technology was implemented to further increase gross die per wafer.
2.7 8-layers 3D Vertical RRAM with Excellent Scalability towards Storage Class Memory Applications, Q. Luo, X. Xu, T. Gong , H. Lv, D. Dong, H. Ma, P. Yuan, J. Gao, J. Liu, Z. Yu, J. Li, S. Long, Q. Liu, M. Liu, Chinese Academy of Sciences, *University of the Chinese Academy of Sciences
For the first time, we experimentally demonstrated a bit cost scalable (BiCS) 8-layer 3D vertical RRAM with ultimate scalability. The design of self-selective cell (SSC) with non-filamentary switching were successfully extended to 8 stacks and exhibits salient features, including high nonlinearity (>102), forming free and high endurance (>107). An extremely scaled 3D structure with 5 nm size and 4 nm vertical pitch was further demonstrated. The sub μA operation current is quite promising for low power applications, but not good for sensing speed. A fixed bitline voltage sensing circuit was proposed to address the latency issue. Sub-μs read latency in bit sensing mode was successfully achieved.