Session 2: Circuit and Device Interaction Advanced Platform Technologies

Monday, December 5, 1:30 p.m
Grand Ballroom B
Co-Chairs: Jun Yuan, Qualcomm
Maarten Vertregt, NXP Semiconductors

1:35 PM
2.1 FPGA Design and System Optimizations with New Technologies (Invited), N. Chong, J. Jing, H. Liu, G. Refai-Ahmed, S. Wu, and X. Wu, Xilinx INC

Recent new technologies, such as HK/MG, multi-patterning, 3D-IC, FinFET and SADP/SAQP, etc. have significant impacts to designs and architectures. Xilinx has been aware of these impacts, and actively improving its FPGA designs and architectures, in order to take the benefits of these technologies while avoiding negative impacts. Several examples will be provided in this article.

2:00 PM
2.2 22nm FDSOI Technology for Emerging Mobile, Internet-of-Things, and RF applications, R. Carter, J. Mazurier*, L. Pirro*, J.-U. Sachse, P. Baars, J. Faul, C. Grass, G. Grasshoff, P. Javorka, T. Kammler, A. Preusse, S. Nielsen, T. Heller, J. Schmid, H. Niebojewski*, P.-Y. Chou, E. Smith, E. Erben, C. Metze, C. Bao, Y. Andee*, I. Aydin*, S. Morvan*, J. Bernard*, E. Bourjot*, T. Feudel, D. Harame, R. Nelluri, H.-J. Thees, L. M. Meskamp, J. Kluth, B. Mulfinger, M. Rashed, R. Taylor, C. Weintraub, J. Hoentschel, M. Vinet*, J. Schaeffer, and B. Rice, Globalfoundries,*CEA-LETI

22FDXTM is the industry’s first FDSOI technology architected to meet the requirements of emerging mobile, Internet-of-Things (IoT), and RF applications. This platform achieves the power and performance efficiency of a 16/14nm FinFET technology in a cost effective, planar device architecture that can be implemented with ~30% fewer masks.

2:25 PM
2.3 First Fully Functionalized Monolithic 3D+ IoT Chip with 0.5 V Light-electricity Power Management, 6.8 GHz Wireless-communication VCO, and 4-layer Vertical ReRAM, F. K. Hsueh, C. H. Shen, J.-M. Shieh, K.-S. Li, H.-C. Chen, W.-H. Huang, H.-H. Wang, C.-C. Yang, T.-Y. Hsieh, C.-H. Lin, B.-Y. Chen, Y.-S. Shiao, G.W. Huang, O.-Y. Wong*, P.-H. Chen*, and W.-K. Yeh, National Nano Device Laboratories, *National Chiao Tung University

For the first time, we report low-cost heterogeneously integrated sub-40nm epi-like Si monolithic internet of thins (IoT) 3D+-IC with wireless communication, light-electricity power management and vertical ReRAM (VRRAM) modules. High current driving multi-channel 3D+ UTB-MOSFETs (2.7/1.5 mA/μm for N/P FETs) was fabricated by low thermal budget super-CMP-planarized visible laser- crystallized epi-like Si channel and CO2 far- infrared laser annealing (CO2-FIR-LA) activation technologies that support a 6.8GHz high frequency VCO circuits, 0.5V low-voltage power management circuit and drives 20nm 4-layer VRRAM (Set/Reset <1.2V/1.8V, 3-bits/cell). This unique TSV-free monolithic 3D+IC process provides the superiority in 3D hetero-integration; we successfully integrate these circuits in a low cost, small footprint, fully functionalized 3D+ IoT chip. 2:50 PM 2.4 A 300mm Foundry HRSOI Technology with Variable Silicon Thickness for Integrated FEM Applications, R. T. Toh, S. Parthasarathy, T. Sun, S. Zhang, P. R. Verma, C. S. Zhu, V. S. Nune, J. S. Wong, M. Govindarajan, Y. K. Yoo, K. W. Chew, and D. S. Ang*, GLOBALFOUNDRIES, *Nanyang Technological University A novel approach to technology integration of system-on-chip RF Front-End Module (FEM) is presented. Device design to achieve best-in-class extended drain power mosfet (EDNMOS) with Ron of 1.6Ohm-mm and fT >39GHz is discussed. This is followed by an analysis of a high performance switch device integrated via selective silicon thinning.

3:15 PM
2.5 A 14nm Finfet Transistor-Level 3D Partitioning Design to Enable High-Performance and Low-Cost Monolithic 3D IC, J. Shi, D. Nayak*, S. Banna*, R. Fox*, S. Samavedam*, S. Samal**, and S. K. Lim**, University of Massachusetts at Amherst, *GLOBALFOUNDRIES, **Georgia Institute of Technology

The conventional monolithic 3D IC (M3D) shows performance degradation compared to 2D IC due to limited thermal budget in fabrication. A transistor-level (TR-L) partitioning design based M3D is used to mitigate this performance degradation and also enable lower cost compared to the conventional M3D that uses the gate-level partitioning scheme.

3:40 PM
2.6 A 7nm CMOS Platform Technology Featuring 4th Generation FinFET Transistors with a 0.027um2 High Density 6-T SRAM cell for Mobile SoC Applications (Late News), S.-Y. Wu, C.Y. Lin, M.C. Chiang, J.J. Liaw, J.Y. Cheng, S.H. Yang, C.H. Tsai, P.N. Chen, T. Miyashita, C.H. Chang, V.S. Chang, K.H. Pan, J.H. Chen, Y.S. Mor, K.T. Lai, C.S. Liang, H.F. Chen, S.Y. Chang, C.J. Lin, C.H. Hsieh, R.F. Tsui, C.H. Yao, C.C. Chen, R. Chen, C.H. Lee, H.J. Lin, C.W. Chang, K.W. Chen, M.H. Tsai, K.S. Chen, Y. Ku, and S.M. Jang, TSMC

4:05 PM
2.7 A 7nm FinFET Technology Featuring EUV Patterning and Dual Strained High Mobility Channels (Late News), R. Xie, P. Montanini*, K. Akarvardar, N. Tripathi, B. Haran*, S. Johnson, T. Hook*, B. Hamieh*, D. Corliss*, J. Wang*, X. Miao*, J. Sporre*, J. Fronheiser, N. Loubet*, M. G. Sung, S. Sieg*, S. Mochizuki*, C. Prindle, S.-C. Seo*, A. Greene*, J. Shearer*, A. Labonte, S. C. Fan*, L. Liebmann, R. Chao*, A. Arceo*, K. Chung*, K. Y. Cheon**, P. Adusumilli*, H. Amanapu*, Z. Bi*, J. Cha**, H.-C. Chen*, R. Conti*, R. Galatage, O. Gluschenkov*, V. Kamineni, K. Kim**, C. Lee*, F. L. Lie*, Z. Liu*, S. Mehta*, E. Miller*, H. Niimi, C. Niu, C. Park, D.-H. Park**, M. Raymond, B. Sahu, M. Sankarapandian*, S. Siddiqui, R. Southwick*, L. Sun, C. Surisetty*, S. Tsai, S. Whang**, P. Xu*, Y. Xu*, C.-C. Yeh*, P. Zeitzoff, J. Zhang, J. Li*, J. Demarest*, J. Arnold*, D. Canaperi*, D. Dunn*, N. Felix*, H. Jagannathan*, S. Kanakasabapathy*, W. Kleemeier, C. Labelle, M. Mottura, P. Oldiges*, S. Skordas*, T. Standaert*, T. Yamashita*, M. Colburn*, M.-H. Na*, V. Paruchuri*, S. Lian**, R. Divakaruni*, T. Gow*, S. Lee**, A. Knorr, H. Bu*, and M. Khare*, GLOBALFOUNDRIES, *IBM, **Samsung