Session 19: Memory Technology Charge Based Memories and Advanced Memories
Tuesday, December 5
Grand Ballroom A
Co-Chairs: Pei-Ying Du, Macronix International Co., Ltd.
Takeshi Yamaguchi, Toshiba Memory Corporation
19.1 A 128Gb (MLC)/192Gb (TLC) Single-Gate Vertical Channel (SGVC) Architecture 3D NAND using only 16 Layers with Robust Read Disturb, Long-Retention and Excellent Scaling Capability, H.-T. Lue, P.-Y. Du, W.-C. Chen, Y.-. Lee, T.-H. Hsu, T.-H. Yeh, K.-P. Chang, C.-C. Hsieh, C. Huang, G.-R. Lee, C.-P. Chen, C.-F. Chen, C.-J. Chiu, Y. J. Chen, W. P. Lu, T. Yang, K.-C. Chen, C.-H. Hung, K.-C. Wang and Chih-Yuan Lu, Macronix International Co., Ltd
We have successfully developed a 128Gb MLC (or 192Gb TLC) 3D NAND Flash using 16-layer SGVC architecture. The produced memory density is 1.6 Gb/mm2 for MLC or 2.4 Gb/mm2 for TLC (including CMOS peripheral area, spared BL’s and blocks). Such memory density is comparable to 48-layer 3D NAND using the popular gate-all-around (GAA) structures. SGVC has the important advantage of much smaller cell size and pitch scaling capability which allows very high-density memory at much lower stacking layer number. SGVC possesses very robust read disturb immunity (>120M read) and long-retention (> 40 years at room temperature) at fresh state that can suppress the very frequent wear-leveling and refresh operations needed for other 3D NAND Flash devices and is very suitable for read-intensive memory. With further stacking/scaling, it is possible to realize low- cost 1Tb single-chip solution at merely 48 layers.
19.2 Lateral Charge Migration Suppression of 3D-NAND Flash by Vth Nearing for Near Data Computing, K. Mizoguchi, S. Kotaki, Y. Deguchi and K. Takeuchi, Chuo University
Vth Nearing is proposed to suppress the lateral charge migration and to improve the reliability of 3D TLC NAND flash. By modulating data so that Vth of adjacent cells become close, data-retention errors decrease by 40%. Data-retention time increases by 2.8-times. The proposal is implemented in the SSD controller.
19.3 Reliability and Scalability of FinFET Split-Gate MONOS Array with Tight Vth Distribution for 16/14nm-node Embedded Flash, S. Tsuda, T. Saito, H. Nagase, Y. Kawashima, A. Yoshitomi, S. Okanishi, T. Hayashi, T. Maruyama, M. Inoue, S. Muranaka, S. Kato, T. Hagiwara, H. Saito, T. Yamaguchi, M. Kadoshima, T. Maruyama, T. Mihara, H. Yanagita, K. Sonoda, T. Yamashita and Y. Yamaguchi, Renesas Electronics Corporation
FinFET SG-MONOS array for 16/14nm-node eFlash is successfully operated and tight Vth distribution is confirmed even after retention. Fin structure enables scaling of the control gate and the memory gate, which is found to lead to the improvement of retention characteristics due to reduction of the program/erase carrier mismatch.
3:15 PM Coffee Break
19.4 Advanced memory solutions for emerging circuits and systems (Invited), B. Giraud, A. Makosiej, R. Boumchedda, N. Gupta, A. Levisse, E. Vianello and J.-P. Noel, University Grenoble Alpes, CEA, LETI, MINATEC
This paper presents the most recent results of LETI memory circuit design activities to address the increasing memory demand due to emerging nomad markets. We have investigated both volatile and non-volatile memory solutions with different technologies such as 3D CoolCubeTM, TFET and ReRAM.
19.5 2D Molybdenum Disulfide (MoS2) Transistors Driving RRAMs with 1T1R Configuration, R. Yang, H. Li, K. K. H. Smithe, T. R. Kim, K. Okabe, E.Pop, J. A. Fan and H.-S. P. Wong, Stanford University
We demonstrate the first 1-transistor-1-resistor (1T1R) memory cell using the monolayer molybdenum disulfide (MoS2) field-effect transistor (FET) and resistive random access memory (RRAM). This 1T1R demonstration realizes a key milestone for tight integration of memory with logic in a monolithic 3D integrated chip.
19.6 Engineering of Ferroelectric Switching Speed in Si Doped HfO2 for High-Speed 1T-FERAM Application, H. K. Yoo, J. S. Kim, Z. Zhu*, Y. S. Choi, A. Yoon*, M. R. MacDonald**, X. Lei**, T. Y. Lee***, D. Lee^, S. C. Chae***, J. Park^, D. Hemker*, J. G. Langan**, Y. Nishi^^^ and S. J. Hong, SK Hynix Inc., *Lam Research Corp., **Versum Materials, ***Seoul Nat. Univ., ^CNR, Institute for Basic Science (IBS), ^^Stanford Univ.
We propose a control of grain size in Si:HfO2 which would lower the Ec, thereby, increase the switching speed for high speed 1T-FERAM application. We successfully demonstrated that Si:HfO2 consists of controlled nano-grains with a FE property of Ec ~0.5MV/cm, which is a half of the ordinary Si:HfO2, and the domain switching speed reaches ~3 times faster than that of ordinary grain sized Si:HfO2.
19.7 A FeFET based super-low-power ultra-fast embedded NVM technology for 22nm FDSOI and beyond, S. Dünkel, M. Trentzsch, R. Richter, P. Moll, C. Fuchs, O. Gehring, M. Majer, S. Wittek, B. Müller, T. Melde, H. Mulaosmanovic*, S. Slesazeck*, S. Müller**, J. Ocker**, M. Noack**, D.-A. Löhr***, P. Polakowski***, J. Müller***, T. Mikolajick*, J. Höntschel, B. Rice, J. Pelleri, and S. Beyer, GLOBALFOUNDRIES Fab1 LLC & Co. KG, *NaMLab gGmbH, **Ferroelectric Memory GmbH, ***Fraunhofer IPMS
A ferroelectric field effect transistor (FeFET) based eNVM solution for a 22nm FDSOI CMOS technology is presented. Memory windows of 1.5V are demonstrated in aggressively scaled FeFET cells (0.025µm²) with endurance up to 10E5 cycles. Complex pattern are written into 32MBit arrays using ultra-fast program/erase pulses in a 10ns range at 4.2V. High temperature retention up to 300°C is achieved.