Session 17: Compound Semiconductor and High Speed 1D and 2D III-V Nanoscale MOSFETs

Tuesday, December 5
Imperial Balroom A
Co-Chairs: Erik Lind, Lund University
Alon Vardi, MIT

9:05 AM
17.1 Record Performance Top-down In0.53Ga0.47As Vertical Nanowire FETs and Vertical Nanosheets, S. Ramesh, Ts. Ivanov*, V. Putcha, A. Alian*, A. Sibaja-Hernandez*, R. Rooyackers*, E. Camerotto**, A. Milenin*, N. Pinna*, S. El Kazzi*, A. Veloso*, D. Lin*, P. Lagrain*, P. Favia*, N. Collaert* and K. De Meyer, KU Leuven, *IMEC, **Lam Research Belgium

We report high performance, dry etched In0.53Ga0.47As vertical nanowire and nanosheet devices, fabricated using VLSI compatible flow. The device exhibit SSmin = 63mV/dec, ION = 397μA/ μm, GmMAX = 1.6mS/μm and Q = 21. A reliability analysis puts these vertical MOSFETs in line with other IIIV devices with similar gate stack.

9:30 AM
17.2 Sub-10 nm Diameter InGaAs Vertical Nanowire MOSFETs, X. Zhao, C. Heidelberger, E. A. Fitzgerald, W. Lu, A. Vardi, and J. A. del Alamo, Massachusetts Institute of Technology

We present the first sub-10 nm diameter vertical nanowire transistors of any kind in any semiconductor system. These devices are InGaAs MOSFETs fabricated by a top-down approach using reactive ion etching, alcohol-based digital etch and Ni alloyed contacts. Record ON current and peak transconductance are obtained in a 7 nm diameter device. Excellent scaling behavior is observed with performance increasing as the diameter is shrunk down to 7 nm.

9:55 AM
17.3 Sub-100-nm Gate-Length Scaling of Vertical InAs/InGaAs Nanowire MOSFETs on Si, O.-P. Kilpi, J. Svensson and L.-E. Wernersson, Lund University

We demonstrate a process to vary the gate-length of vertical InAs/InGaAs MOSFETs on the same sample with high accuracy. The devices have gate-length ranging from 25 to 140 nm. We demonstrate a record vertical MOSFET with gm=2.4 mS/µm and a device with Ion=407 µA/µm at Ioff=100 nA/µm and VDD=0.5V.

10:20 AM
17.4 High Mobility In0.30Ga0.70As MOSHEMTs on Low Threading Dislocation Density 200 mm Si Substrates: A Technology Enabler Towards Heterogeneous Integration of Low Noise and Medium Power Amplifiers with Si CMOS, S. Yadav, A. Kumar, X. S. Nguyen*, K. H. Lee*, Z. Liu*, W. Xing*, S. Masudy-Panah, K. Lee*, C. S. Tan*, E. A. Fitzgerald*, D.A. Antoniadis*, Y.-C. Yeo and X. Gong, ECE, NUS, *SMART-LEES

Heterogeneous integration of In0.30Ga0.70As MOSHEMTs and Si-CMOS in 200 mm wafer scale is proposed. HEMT epitaxial layers with threading dislocation density of lower than 2 × 107 cm-2 are demonstrated using MOCVD and an effective mobility of 4900 cm2/V·s at sheet carrier density of 3 × 1012 cm-2 is achieved.

10:45 AM Coffee Break

11:10 AM
17.5 A Scaled Replacement Metal Gate InGaAs-on-Insulator n-FinFET on Si with Record Performance, H. Hahn, V. Deshpande, E. Caruso*, S. Sant**, E. O’Connor, Y. Baumgartner, M. Sousa, D. Caimi, A. Olziersky, P. Palestri*, L. Selmi*, A. Schenk** and L. Czornomaz, IBM Research GmbH Zürich Laboratory, *University of Udine, **ETH Zurich

We demonstrate a scaled replacement-metal-gate InGaAs-on-Insulator n-FinFET on Si with Lg = 13 nm and record record ION of 249 µA/µm at fixed IOFF = 100 nA/µm and VD = 0.5 V. A subthreshold swing in saturation of 89 mV/dec and a Ron of 355 Ohm.µm is also achieved. We further investigate the transport mechanisms at play in order to shed light on the contribution from short-channel effects and carrier generation and recombination mechanisms on SS and IOFF, at such a short gate length, using calibrated full 3D and simplified 2D TCAD simulations.

11:35 AM
17.6 Self-Aligned InGaAs FinFETs with 5-nm Fin-Width and 5-nm Gate-Contact Separation, A. Vardi, L. Kong, W. Lu, X. Cai, X. Zhao, J. Grajal and J. del Alamo, Massachusetts Institute of Technology

We demonstrate self-aligned InGaAs FinFETs with fin widths down to 5 nm fabricated through a CMOS compatible front-end process. Precision dry etching of the recess cap results in metal contacts that are about 5 nm away from the intrinsic portion of the fin. The new process has allowed us to fabricate devices with undoped fins and compare them with delta-doped fins.

12:00 PM
17.7 10-nm Fin-Width InGaSb p-Channel Self-Aligned FinFETs Using Antimonide-Compatible Digital Etch, W. Lu, I. P. Roh*, D.-M. Geum*, S.-H. Kim*, J. D. Song*, L. Kong and J. A. del Alamo, Massachusetts Institute of Technology, *Korea Institute of Science and Technology

We demonstrate the first InGaSb p-channel FinFET with a narrowest fin width of 10 nm, a gate length of 20 nm, and a fin width/channel thickness aspect ratio > 2. To fabricate such devices, a new antimonide-compatible digital etch has been developed. 10 nm Wf transistor exhibits record gm = 160 uS/um and gm/Wf = 704 uS/um, with much improved subthreshold characteristics.