IEDM

Session 14: Process and Manufacturing Technology Interconnect Patterning and Memory Integration

Tuesday, December 5
Continental Ballroom 5
Co-Chairs: Hsin-Ping Chen, TSMC
John Dukovic, Applied Materials

9:05 AM
14.1 20 Years of Cu BEOL in Manufacturing, and its Future Prospects (Invited), D. Edelstein, IBM TJ Watson Research Center

This year marks the 20th anniversary of IBM’s an-nouncement of its impending plans to insert CMOS/Cu BEOL technology into production, and its having shipped the first functional CPU prototypes. The subsequent manufacturing ramp in mid-1998 provided the first commercial IC chips with Cu BEOL. This invited paper covers the timeline of this tech-nology, with its key defining elements, subsequent innova-tions, and likely future directions. The original, basic features of this technology have endured to this day, though with many evolutionary improvements. But now, in its 10th generation of manufacturing, and 12th in research, we are finally seeing changes beyond evolutionary. The replacement of Cu metal for the finest wiring levels may occur over the next 1-3 nodes.

9:30 AM
14.2 Fully Aligned Via Integration for Extendibility of Interconnects to Beyond the 7 nm Node, B. D. Briggs, C. B. Peethala, D. L. Rath*, J. Lee, S. Nguyen, N. V. LiCausi***, P. S. McLaughlin*, H. You**, D. Sil, N. A. Lanzillo, H. Huang, R. Patlolla, T. Haigh Jr, Y. Xu, C. Park***, P. Kerber*, H. K. Shobha, Y. Kim^, J. Demarest, J. Li, G. Lian**, M. Ali**, C. t Le**, E. T. Ryan***, L. A. Clevenger, D. F. Canaperi, T. E. Standaert, G. Bonilla, and E. Huang, IBM at Albany Nanotech, *IBM T.J. Watson Res. Ctr., **IBM Systems, ***GLOBALFOUNDRIES, ^Samsung Electronics

A novel fully aligned via (FAV) BEOL integration scheme is demonstrated at 36 nm pitch, with extendibility to beyond the 7 nm node. FAV enables full control of via/line CD and edge placement, which in turn enables essential resistance and reliability benefits for post 7 nm BEOL wiring.

9:55 AM
14.3 All-Carbon Interconnect Scheme Integrating Graphene-Wires and Carbon-Nanotube-Vias, J. Jiang, J. Kang, J. H. Chu and K. Banerjee, University of California, Santa Barbara

An “all-carbon” interconnect scheme that integrates horizontal multilayer graphene wires and vertical carbon-nanotube vias is demonstrated for the first time. The hybrid interconnect scheme is shown to surpass copper in terms of performance, energy efficiency, and reliability down to 5-nm node, paving the way for carbon nanomaterials in VLSI technology.

10:20 AM Coffee Break

10:45 AM
14.4 Continuing Moore’s Law with EUV Lithography (Invited), B. Turkot, S. Carson and A. Lio, Intel Corp.

Extreme Ultra-Violet (EUV) lithography, with its exposure wavelength of 13.5nm, offers a compelling alternative to 193nm-immersion lithography, improving imaging resolution and reducing a key contribution to Edge Placement Error (EPE). Recently, significant progress has been made in the development of EUV exposure tools, with source power meeting the roadmap target for EUV insertion1 as well as demonstrating improvements in system availability and infrastructure such as mask blank defectivity, pellicle membrane manufacturing, and EUV photoresist materials. This paper reviews the current status and challenges of EUV lithography for High Volume Manufacturing (HVM).

11:10 AM
14.5 Electron Beam Detection of Cobalt Trench Embedded Voids Enabling Improved Process Control for Middle-Of-Line at the 7nm Node and beyond, N. Breil, D. Shemesh, J. Fernandez, R. Hung, N. Bekiaris, J. Tseng, M. Naik, J.H. Park, J. Bakke, A. Kumar, K. Nafisi, A. Litman, A. Karnieli, V. Kuchik, A. Wachs, N. Khasgiwale and M. Chudzik, Applied Materials

Inline detection of embedded voids within Middle- Of-Line (MOL) cobalt metal lines is a major industry gap at 7nm technology node and below, for both developing the new metallization solutions, as well as for monitoring during ramp and production. We present a new non-destructive electron beam cobalt void detection method, leveraging an improved scanning electron microscope (SEM) imaging technique, which enable an accurate detection of voids embedded inside MOL metal trenches. After explaining the potential process mechanisms causing void formation, we introduce the e-beam technique, and demonstrate by simulation and experiments the correlation between the electron signal and the volume and depth of the voids. We conclude this paper by discussing how a defect inspection strategy using a massive metrology approach can lead to a faster and more efficient development of the Cobalt metallization.

11:35 AM
14.6 Improvement of HfO2 based RRAM array performances by local Si implantation, M. Barlas, A. Grossi, L. Grenouillet, E. Vianello, E. Nolot, N. Vaxelaire, P. Blaise, B. Traoré, J. Coignus, F. Perrin, R. Crochemore, F. Mazen, L. Lachal, S. Pauliac, C. Pellissier, S. Bernasconi, S. Chevalliez, J.F. Nodin, L. Perniola, E. Nowak, CEA-Leti, Minatec

A thorough insight of Si implantation in HfO2- based OXRAM is presented, from a material standpoint up to a 4 kbit 1T-1R array. We demonstrate for the first time that local implantation enables switching area localization and significantly decreases forming, set and reset voltages, improves data retention (tails at 3sigma are stable up to 1000 min at 165°C), while not being detrimental for endurance. In particular using low voltage programming conditions (VF < 3V with 100 ns pulses), a memory window of 10 at 3sigma is demonstrated, paving the way to low power OxRAM arrays with lower variability and improved robustness.