Session 14: Modeling and Simulation 2D Materials and Organic Electronics

Tuesday, December 6, 9:00 a.m.
Continental Ballroom 7-9
Co-Chairs: John Robertson, Cambridge University
Yang Liu, Zhejiang University

9:05 AM
14.1 Two-Dimensional Transistors Based on MoS2 Lateral Heterostructures, D. Marian, E. Dib, T. Cusati, A. Fortunelli*, G. Iannaccone and G. Fiori, University of Pisa, *CNR-ICCOM

We propose two transistor architectures based on lateral heterostructures of metallic and semiconducting phases of monolayer MoS2, whose patterning has been demonstrated via e-beam irradiation: i) lateral heterostructure FET and ii) “planar barristor”, the 2D counterpart of the graphene barristor. We evaluate their performance with ab-initio simulations against the ITRS.

9:30 AM
14.2 Physics of Electronic Transport in Two-dimensional Materials for Future FETs (Invited), M. Fischetti and W. Vandenberghe, The University of Texas at Dallas

We discuss some basic physical properties of electron transport in two-dimensional materials. First, we discuss how the predicted thermodynamic instability of 2D crystals may influence charge transport via the coupling of electrons with acoustic flexural modes. We then review the properties of suspended and supported graphene and its ribbons and consider the problem of evaluating correctly the electron-phonon coupling in the case of phosphorene. Finally, we discuss the main features of 2D topological insulators and their possible use in transistors.

9:55 AM
14.3 A Numerical Study of Si-TMD Contact with n/p Type Operation and Interface Barrier Reduction for Sub-5nm Monolayer MoS2 FET, Y.-T. Tang, K.-S. Li, L.-J. Li*, M.-Y. Li*, C.-H. Lin, Y.-J. Chen, C.-C. Chen, C.-J. Su, B.-W. Wu, C.-S. Wu, M.-C. Chen, J.-M. Shieh, W.-K. Yeh, P.-C. Su**, T. Wang**, F.-L. Yang*** and C. Hu^, National Nano Device Laboratories, &King Abdullah University of Science and Technology, **National Chiao-Tung University, ***Academia Sinica, ^University of California, Berkeley

An atomic-scale numerical study of Si contact with transition metal dichalcogenides (TMD) semiconductor materials is proposed by first-principles simulation for the first time. The monolayer MoS2 channel can be operated as both of n- and p-type FET by properly doping Si S/D to adjust the TMD channel potential. The gradient MoSx junction of dichalcogenide vacancies enables Si-MoS2 contact resistance lower than 100Ω-μm for interface Schottky barrier height reduction. The compact Si-MoS2 interface study can potentially provide monolayer TMD contact design guideline for the sub-5 nm TMD FET fabrication technology.
10:20 AM
14.4 A Modified Schottky Model for Graphene-semiconductor (3D/2D) Contact: A Combined Theoretical and Experimental Study, S.-J. Liang, W. Hu*, A. Di Bartolomeo**, S. Adam*** and L. K. Ang, Singapore University of Technology and Design, *Lawrence Berkeley National Laboratory Berkeley, **Universita’ degli Studi di Salerno, ***National University of Singapore and Yale-NUS College

We present a theoretical and experimental study of graphene/semiconductor (3D/2D) contacts for different semiconductors and dimensionalities, and we propose a revised Schottky model for graphene/semiconductor contact, which is validated by first-principle calculations and experiments. The proposed model offers new perspective on the nature of graphene/semiconductor contact.

10:45 AM
14.5 Performance Predictions of Single-layer In-V double-gate n- and p-type Feld-effect Transistors, H. Carrillo-Nuñez, C. Stieger, M. Luisier and A. Schenk, ETH Zurich

Through ab-initio quantum transport simulations the logic performance of single-layer InAs, InN, InP, and InSb III-V compounds is analyzed in this paper for n- and p-type applications. The key findings are that (i) the low electron effective masses of all these materials lead to very similar and attractive ON-currents in n-type transistors, but cause a rapid deterioration of their sub-threshold swing as the gate length shrinks to 10 nm and below, (ii) the p-type devices show much smaller and scattered current values that are too low to eventually challenge Si FinFETs, and (iii) the density-of-states bottleneck effect strongly influences the behavior of the n-type devices.

11:10 AM
14.6 Current Status and Challenges of the Modeling of Organic Photodiodes and Solar Cells (Invited), R. R. Clerc, B. Bouthinon*, M. Mohankumar**, P. Rannou**, J. Vaillant***, T. Maindron***, B. Racine***, Y.-F. Chen^, L. Hirsch^, J.-M. Verilhac^^, A. Pereira^^ and A. Revaux^^, Institut d Optique Graduate School, CNRS *ISORG, **INAC, CEA, ***CEA LETI, ^University of Bordeaux, ^^CEA, LITEN

Progress in the modeling of charge transport in solution processed solar cells and photodiodes is reviewed. Through several examples involving modeling and original experiments, the role of intentional doping, structural defects and oxygen contamination is discussed.

11:35 AM
14.7 Prospects of Ultra-thin Nanowire Gated 2D-FETs for Next-Generation CMOS Technology, W. Cao, W. Liu and K. Banerjee, University of California, Santa Barbara

A core/shell nanowire gated sub-20 nm 2D-FET, targeted at addressing the ultra-thin dielectric growth and channel formation challenges of nanoscale 2D-FETs is demonstrated. Rigorous quantum transport simulations are employed to uncover the full potential of this novel device, as well as to provide guidance to subsequent device design and optimization.