IEDM

Session 13: Modeling and Simulation Modeling and Simulation of Advanced CMOS Transistors

Tuesday, December 5
Continental Ballroom 1-3
Co-Chairs: Geert Eneman, imec
Lee Smith, Synopsys

9:05 AM
13.1 Hot-Carrier Degradation in FinFETs: Modeling, Peculiarities, and Impact of Device Topology, A. Makarov, S. Tyaginov, B. Kaczer*, A. Chasin*, A. Grill, G. Hellings*, M. Vexler**, D. Linten* and T. Grasser, Vienna Technical University, *imec, **A.F. Ioffe Inst.

We perform a comprehensive analysis of hot- carrier degradation (HCD) in FinFETs. To accomplish this goal we employ our physics-based HCD model and validate it against experimental data acquired in n-FinFETs with a channel length of 28 nm. We use this verified model to study the distribution of the trap density across the fin/stack interface. The methodology is applied to analyze the effect of transistor architectural parameters, namely fin length, width, and height, on HCD. Our results show that at the same conditions HCD becomes more severe in shorter devices and in transistors with wider fins, while the impact of the fin height on the damage is weak. Finally we demonstrate that a proper HCD description can be achieved only with a physics- based model.

9:30 AM
13.2 Performance comparison for FinFETs, Nanowire and Stacked Nanowires FETs: Focus on the influence of Surface Roughness and Thermal Effects, O. Badami, F. Driussi, P. Palestri, L. Selmi, and D. Esseni, University of Udine

We perform a comprehensive comparison of FinFETs, stacked nanowires (stacked NWs), circular and square gate-all-around (GAA) 𝑛-FETs with same footprint, by using an in-house deterministic BTE solver accounting for quantum confinement, a wide set of scattering mechanisms and self-heating. We show that an increase in surface roughness (SR) can frustrate the improvement in on current, Iπ‘œπ‘›, that for high-quality interfaces we observe in stacked NWs compared to FinFETs. Simulations suggest that SR also influences whether or not In0.53Ga0.47As can provide better Iπ‘œπ‘› than strained silicon (sSi).

9:55 AM
13.3 Monte Carlo Benchmark of In0.53Ga0.47As- and Silicon-FinFETs, F. Bufler, G. Eneman, N. Collaert, A. Mocuta, imec

Monte Carlo simulation reproducing measured transfer characteristics of FinFETs with LG=20 nm and W=9 nm shows that InGaAs has similar performance as Si for Vdd of 0.5 V. However, ideal InGaAs-FinFETs loose all advantage upon reducing W to 5 nm because of a charge reduction due to n-type channel doping.

10:20 AM Coffee Break

10:45 AM
13.4 Modelling nanoscale n-MOSFETs with III-V compound semiconductor channels: from advanced models for band structures, electrostatics and transport to TCAD (Invited), L. Selmi, E. Caruso, S. Carapezzi*, M. Visciarelli*, E. Gnani*, N. Zagni**, P. Pavan**, P. Palestri, D. Esseni, A. Gnudi*, S. Reggiani*, F.M. Puglisi**, G. Verzellesi**, University of Udine (DPIA), *University of Bologna, **University of Modena e Reggio Emilia

We review a few state of the art solutions and recent developments to model short channel III-V compound semiconductor n-MOSFETs based on full quantum transport, semiclassical multi-valley / multi-subband transport and TCAD models. The pros and cons of each, and the insights they can deliver, are illustrated with examples from recent technology developments and literature. Areas where improvements and implementations at TCAD level are most necessary are highlighted as well.

11:10 AM
13.5 Ferroelectric Transistor Model based on Self-Consistent Solution of 2D Poisson’s, Non-Equilibrium Green’s Function and Multi-Domain Landau Khalatnikov Equations, A. Saha, P. Sharma*, I. Dabo, S. Datta* and S. Gupta, Penn State University, *University of Notre Dame

We present a physics-based model for FEFETs/ NCFETs without an inter-layer metal between ferroelectric and dielectric in the gate stack. The model self-consistently solves 2D Poisson’s equation, NEGF based charge and transport equations, and multi-domain Landau Khalatnikov (LK) equations with the domain interaction term. The proposed simulation framework captures the variation of FE polarization along the gate length due to non-uniform electric field along the channel. To calibrate the LK equations, we fabricate and characterize 10nm HZO films. Based on the calibrated model, our results highlight the importance of larger domain interaction to boost the benefits of FEFETs with subthreshold swing (SS) as small as ~50mV/decade achieved at room temperature. As domain interaction increases, the characteristics of FEFETs without inter-layer metal approach those of FEFETs with inter-layer metal.

11:35 AM
13.6 A New Framework of Physics-Based Compact Model Predicts Reliability of Self-Heated Modern ICs: FinFET, NWFET, NSHFET Comparison, W. Ahn, C. Jiang, J. Xu* and M. A. Alam, Purdue University, *Tsinghua University

Self-heating effects (SHE) has emerged as an unfortunate corollary of confined-gate transistors (e.g. FinFET; Nanowire-FET, NWFET; NanoSheet-FET, NSHFET) needed for electrostatically-robust sub- 10nm ICs [1-3]. The IC-specific SHE reflects increasing thermal resistances (R_th) associated with all three tiers (i.e., transistor, circuit, and system) of the hierarchy. Many groups have developed tier-specific thermal models, which can neither predict the junction temperature (T_J) accurately nor suggest innovative strategies to reduce T_J by identifying/removing thermal bottlenecks in the hierarchy. In this paper, we develop computationally efficient, physics-based compact models for each tier, and then stack them to estimate T_J-dictated performance/reliability of sub-10nm technologies. Specifically, we (i) refine thermal compact model for front-end-of-line (FEOL) level (TCM_F) based on 3D FEM transient thermal simulations; (ii) investigate SHE by BSIM- CMG circuit simulation for ICs with refined FEOL model; (iii) develop a physics-based thermal compact model for back-end-of line (BEOL) interconnects and interposers (TCM_B) by using image charge and effective medium theory (EMT). The TCM_F and TCM_B are then integrated to predict T_j-specific ICs reliability (i.e., NBTI, HCI, EM) for 14, 201710, and 7nm FinFETs, NWFETs, and NSHFETs; and finally (iv) we propose various mitigation strategies using thermal shunts to suppress SHE. Our work demonstrates that NSHFET is a good candidate at sub-10nm nodes considering both lower subthreshold swing (SS) than that of FinFET and better reliability than that of NWFET.