Session 12: Circuit and Device Interaction Circuit-Device Challenges in More Moore and More than Moore

Tuesday, December 5
Grand Ballroom B
Co-Chairs: Greg Yeric, ARM
James Chen, TSMC

9:05 AM
12.1 Twin Mode NV Logic Gates for High Speed Computing System on 16nm FINFET CMOS Logic Process, W.-Y. Chien, T.-M. Wang, Y.-D. Chih*, J. Chang*, C. J. Lin, Y.-C. King, National Tsing Hua University, *Taiwan Semiconductor Manufacturing Company

A twin-mode non-volatile logic gates allowing multiple logic functions to be obtained by controlling its non-volatile states is proposed for the first time. This floating metal gate based cell consisting of an inverter controlled by slot contact inputs is successfully demonstrated by standard FinFETs processes in a 16nm technology node. This new twin-mode gates can not only enable reconfiguration capability for logic systems at a gate level, but also prompt the realization of tunable ring oscillators, for multi-functional IOT applications.

9:30 AM
12.2 A Novel PUF Against Machine Learning Attack: Implementation on a 16 Mb RRAM Chip, Y. Pang, H. Wu, B. Gao, D. Wu, A. Chen*, H. Qian, Tsinghua University, *Semiconductor Research Corporation

Physical unclonable function (PUF) is an important hardware security primitive. This paper proposes a novel PUF design based on a double-layer RRAM array architecture and digital RRAM programming achieved by splitting resistance distribution after a continuous distribution was formed. The proposed PUF was implemented on a 16 Mb RRAM test chip and its randomness was verified with NIST test suite. The experimental results demonstrate strong reliability and significantly enhanced resistance against machine learning attack of this novel PUF design.

9:55 AM
12.3 Large-Scale Terahertz Active Arrays in Silicon Using Highly-Versatile Electromagnetic Structures (Invited), C. Wang, Z. Hu, G. Zhang, J. Holloway and R. Han, Massachusetts Institute of Technology

The high integration capability of silicon technologies, as well as the small wavelength of terahertz (THz) signals, make it possible to build a high-density, very-large-scale active THz array on a single chip. This is, however, very challenging in practice, due to the low device efficiency and large footprint of conventional circuit designs. To address these problems, we introduce a set of compact while versatile circuits, which utilize the multi-mode behaviors from structures with tight device-electromagnetic integration. These circuits have enabled large-scale (1) homogeneous arrays for high-power, collimated radiation, and (2) heterogeneous arrays for fast broadband spectral scanning. In particular, 0.1-mW power generation (20-mW effective isotropically-radiated power) at 1 THz, simultaneous transmit/receive capability, and high-parallelism molecular spectroscopy are demonstrated. New opportunities that these works bring about are also discussed.

10:20 AM Coffee Break

10:45 AM
12.4 Variability- and Reliability-Aware Design for 16/14nm and Beyond Technology (Invited), R. Huang1, X. B. Jiang, S. F. Guo, P. P. Ren, P. Hao, Z. Q. Yu, Z. Zhang, Y. Y. Wang, R. S. Wang, Peking University

Device variability and reliability are becoming increasingly important for nano-CMOS technology and circuits, due to the shrinking circuit design margin with the downscaling supply voltage (Vdd). Therefore, robust design should have the awareness of both variability and reliability. In FinFET technology, strong correlation between the variations of device electrical parameters is found, due to the larger impacts of line-edge roughness (LER) in FinFET structure. Accurate compact models and new design methodology for random variability in FinFETs were proposed for the variation- and correlation-aware design. For the reliability awareness, the impacts of BTI-induced temporal shift and the layout dependent aging effects should be taken into account for the optimization of end-of- life (EOL) performance/power/area (PPA). New- generation aging model and circuit reliability simulator for FinFETs were proposed and developed in industry-standard EDA tools. Future challenges are also pointed out, such as statistical BTI and RTN. The results are helpful for the robust and resilient design for 16/14nm and beyond.

11:10 AM
12.5 A Novel Bit-Level Characterization Methodology to Benchmark The FinFET based SRAM Performance Under The Influence of Leakage Current, J.C. Liu, S. Mukhopadhyay, Y.F. Wang, Y.S. Tsai, S.C. Chen, J.H. Lee, Ryan Lu, Y.-H. Lee, and J. He, Taiwan Semiconductor Manufacturing Company

Leakage current due to intrinsic or extrinsic device failure can severely impact the 6-T SRAM performance. This study introduces a ‘Pseudo- Leakage’ current source in the SRAM circuit and takes a pragmatic approach to analyze the possible impact on the overall SRAM performance matrices which are affected by such leakage issues.

11:35 AM
12.6 TSV-free FinFET-based Monolithic 3D+-IC with Computing-in-Memory SRAM Cell for Intelligent IoT Devices, F.-K. Hsueh, H.-Y. Chiu*, C.-H. Shen, J.-M. Shieh, Y.-T. Tang, C.-C. Yang, H.-C. Chen, W.-H. Huang, B.-Y. Chen, K.-M. Chen, G.-W. Huang,W.-H. Chen*, K.-H. Hsu*, S. .R Srinivasa**, N. Jao**, A. Lee***, H. Lee***, V. Narayanan**, K.-L. Wang***, M.-F. Chang* and W.-K. Yeh,
National Nano Device Laboratories, *National Tsing Hua University, **The Pennsylvania State University, ***University of California at Los Angeles

This paper presents the first monolithic 3D vertical cross-tier computing-in-memory (CIM) SRAM cell fabricated using low cost TSV-free FinFET- based 3D+-IC technology. The 9T 3D CIM SRAM cell is able to compute NAND/AND, OR/NOR and XOR/XNOR operations within a single memory cycle. We fabricated stackable multi-fin single-grained Si FinFET using low thermal-budget CO2 far-infrared laser annealing (FIR-LA) for activation and self- aligned silicide. The proposed device achieved high Ion (320 uA/um (n-FET) and 275 uA/um (p-FET)) and high Ion/Ioff (>107). The proposed scheme enables the fabrication of energy and area efficient circuits for cost-aware intelligent IoT devices. For proposed 9T CIM SRAM cell, the monolithic 3D device reduces area overhead by 51%, compared to the 2D version, thanks to the stacking of three additional transistors above the 6T SRAM cell.