Session 11: Memory Technology Charge Based Memories and Scaling

Tuesday, December 6, 9:00 a.m.
Continental Ballroom 4
Co-Chairs: Han Zhao, Intel
Sungyong Chung, SK Hynix

9:05 AM
11.1 First Demonstraion of FinFET Split-Gate MONOS for High-Speed and Highly-Reliable Embedded Flash in 16/14nm-node and Beyond, S. Tsuda, Y. Kawasima, K. Sonoda, A. Yoshitomi, T. Mihara, S. Narumi, M. Inoue, S. Nuranaka, T. Maruyama, T. Yamashita, Y. Yamaguchi and D. Hisamoto*, Renesas Electronics Corporation, *Hitachi, Ltd

FinFET split-gate metal-oxide nitride oxide silicon (SG-MONOS) Flash memories have been fabricated and operated for the first time. Excellent subthreshold characteristics and small threshold-voltage variability owing to a Fin-structure are clarified. It is demonstrated that Fin top-corner effects are well suppressed by incremental step pulse programming for source side injection. Highly reliable data retention at 150 ºC after 250K program/erase cycles is confirmed for the advanced automotive system applications.

9:30 AM
11.2 A New Ruler on the Storage Market : 3D-NAND Flash for High-density Memory and its Technology Evolutions and Challenges on the Future (Invited), J. Lee, J. Jang, J. Lim, Y. G. Shin, K. Lee and E. Jung, Samsung Electronics

Scaling limitations in planar-NAND cell are discussed, including the depletion of floating gate and anomalous programming behavior. It is inevitable to have a paradigm shift to 3D-NAND due to numerous scaling limitations of planar NAND. However, the process complexity also increases in 3D-NAND as the mold height goes up in an exponential trend. Thus, scaling down of mold pitch is required, which degrades the cell characteristics. COP (Cell over Peripheral) 3D- NAND architecture has been developed as an area- scaling technology. CSL (Common-Source Line) junction leakage and p+ junction leakage at peripheral transistors have been improved by increasing the grain size and the thickness of barrier metal, respectively.

9:55 AM
11.3 Polycrystalline-Silicon Channel Trap Induced Transient Read Instability in a 3D NAND Flash Cell String, W.-J. Tsai, W. L. Lin, C. C. Cheng, S. H. Ku, Y. L. Chou, L. Liu, S. W. Hwang, T. C. Lu, K. C. Chen, T. Wang* and C.-Y. Lu, Macronix International Company, LTD., *National Chiao-Tung University

Vt instability caused by grain-boundary trap (GBT) in the poly-crystalline silicon (poly-Si) channel of a 3D NAND string are comprehensively studied. Experimental results reveal that trapping/detrapping of GBT would cause transient cell current with a time constant of 10us or longer, and this transient is strongly affected by the bias history. Sensing offset between program/erase verify (PV/EV) and read (RD) results in “pseudo” charge loss/gain that reduces the sensing margin. Modified EV, PV, or RD bias schemes are suggested to mitigate this effect.

10:20 AM
11.4 Automotive Requirements to Non-Volatile Memories – A Holistic Approach to Qualificaton (Invited), V. Kottler, Robert Bosch GmbH, Automotive Electronics

This work describes a holistic approach to the application of the Robustness Validation methodology to the qualification of non-volatile memories (NVM) for automotive applications, as well as the resulting requirements to the NVM supplier and to the NVM design and technology.

10:45 AM
11.5 A 28nm HKMG Super Low Power Embedded NVM Technology Based on Ferroelectric FETs, M. Trentzsch, S. Flachowsky, R. Richter, J. Paul, B. Reimer, D. Utess, S. Jansen, H. Mulaosmanovic*, S. Müller*, S. Slesazeck*, J. Ocker*, M. Noack*, J. Müller**, P. Polakowski**, J. Schreiter***, S. Beyer, T. Mikolajick^ and B. Rice, GLOBALFOUNDRIES Fab1, * NaMLab gGmbH, ** Fraunhofer IPMS, *** Racyics GmbH, ^ TU Dresden

A ferroelectric field effect transistor (FeFET) based eNVM was successfully implemented into a 28nm HKMG 28SLP CMOS platform. The electrical baseline properties remain the same for the FeFET integration and the JTAG-controlled 64 kbit memory shows clearly separated states. High temperature retention is demonstrated and endurance up to 100.000 cycles was achieved.

11:10 AM
11.6 How to Make DRAM non-volatile? Anti-ferroelectrics: A New Paradigm for Universal Memories, M. Pesic, S. Knebel, M. Hoffmann, C. Richter, T. Mikolajick and U. Schroeder, NaMLab gGmbh

We propose a simple way how non-volatility can be achieved in state-of-the-art ZrO2 based DRAM stacks. By employing electrodes with different workfunction values, a built-in bias is introduced within the dielectric stack to modify the anti-ferroelectric property of ZrO2 from standard volatile to non-volatile behavior with high endurance strength.

11:35 AM
11.7 Fully BEOL Compatible TaOx-based Selector with High Uniformity and Robust Performance, Q. Luo, X. Xu, H. Lv, T. Gong, S. Long, Q. Liu, H. Sun, L. Li, N. Lu and M. Liu, Institute of Microelectronics, Chinese Academy of Sciences

We report a novel TaOx-based selector with trapezoidal band structure, formed by rapid thermal annealing in O2 plasma. Salient features were successfully achieved, such as high current density (1MA/cm2), high selectivity (5×104), low off-state current (~10 pA), robust endurance (>1010), self- compliance and excellent uniformity. The device is composed of fully CMOS-compatible materials and has no thermal budget compatibility concerns. Furthermore, the selector was fabricated in 1kb crossbar array and the integrated 1S1R device shows high nonlinearity in low resistance state (LRS), which is quite effective to solve the sneaking current issue. The demonstrated high performance selector device here shows high potential on manufacturing large scale crossbar array.