IEDM

Welcome to the Editor Press Center. The following press materials may be downloaded from this site for news coverage of the 2019 IEDM.

Chris Burke
co-Media Relations Director
1 919 872 8172
chris.burke@btbmarketing.com

Gary Dagastine
co-Media Relations Director
+1 518 785 2724
gdagastine@nycap.rr.com

Hilton San Francisco Union Square
333 O’Farrell Street
San Francisco, CA USA
December 7-11, 2019

Welcome to the Editor Press Center. Check back periodically for photo and caption updates. The following press materials may be downloaded from this site for news coverage of the IEDM:

San Francisco, CA image (JPEG)
2019 65th IEDM Logo (JPEG)

2019 IEDM Photos with captions:
Selected images from the abstracts are presented in two formats:
– Word file with images associated with a highlighted paper and the caption
– JPEG file with individual high-resolution Images

Image With Caption
Paper #2.4 – “2MB Array-Level Demonstration of STT-MRAM Process and Performance Towards L4 Cache Applications,” J.G. Alzate et al, Intel
High Resolution Images
2.4 Figure 4.jpg
2.4 Figure 7.jpg

Image With Caption
Paper #3.3 – “Monolithic SRAM-CIM Macro Fabricated with Stackable Gate-All-Around MOSFETs,” F.K. Hsueh et al, Taiwan Semiconductor Research Institute/National Chiao Tung Univ/UC-Berkeley
High Resolution Images
3.3 Figure 3.jpg
3.3 Figure 13.jpg
3.3 Figure 16.jpg
3.3 Table 1.jpg

Image With Caption
Paper #4.1 – “1200 V Multi-Channel Power Devices with 2.8 Ω⋅mm ON-Resistance,” J. Ma et al, EPFL/Enkris Semiconductor
High Resolution Images
4.1 Figure 1.jpg
4.1 Figure 8.jpg

Image With Caption
Paper #4.4, “GaN-on-SOI: Monolithically Integrated All-GaN ICs for Power Conversion,” X. Li et al, Imec/KU Leuven
High Resolution Images
4.4 Figure 1.jpg
4.4 Figure 2.jpg
4.4 Figure 13.jpg

Image With Caption
Paper #7.4 – “Equivalent Oxide Thickness (EOT) Scaling with Hafnium Zirconium Oxide High-k Dielectric Near Morphotropic Phase Boundary,” K. Ni et al, Univ. Notre Dame/Purdue Univ./Kurt J. Lester Co
High Resolution Images
7.4 Figure 5.jpg
7.4 Figure 7.jpg
7.4 Figure 8a.jpg

Image With Caption
Paper #9.1 – “First Demonstration of III-V HBTs on 300mm Si Substrates Using Nano-Ridge Engineering,” A. Vais et al, Imec/KU Leuven
High Resolution Images
9.1 Figure 3.jpg
9.1 Figure 10.jpg

Image With Caption
Paper #11.1 – “Vertical Nanowire and Nanosheet FETs: Device Features, Novel Schemes for Improved Process Control and Enhanced Mobility, Potential for Faster & More Energy-Efficient Circuits,” A. Veloso et al, Imec
High Resolution Images
11.1 Figure 23.jpg
11.1 Figure 24.jpg
11.1 Figure 31.jpg

Image With Caption
Paper #14.3 – “Fully Integrated Spiking Neural Network with Analog Neurons and RRAM Synapses,” A. Valentian et al, CEA-Leti
High Resolution Images
14.3 Figure 01.jpg
14.3 Figure 10.jpg
14.3 Figure 14.jpg

Image With Caption
Paper #17.3 – “3D Heterogeneous Integration of High-Performance High-k Metal Gate GaN NMOS and Si PMOS Transistors on 300mm High-Resistivity Si Substrate for Energy-Efficient and Compact Power Delivery, RF (5G and Beyond) and SoC Applications,” H. W. Then et al, Intel
High Resolution Images
17.3 Figure 1.3.jpg
17.3 Figure 6.3.jpg
17.3 Figure 7.3.jpg
17.3 Figure 21.3.jpg

Image With Caption
Paper #18.2 – “Highly Sensitive Slip Sensing Imager for Forceps Grippers Used Under Low Friction Condition,” K. Ando et al, Kagawa Univ./Takamatsu Red Cross Hospital
High Resolution Images
18.2 Figure 1.jpg
18.2 Figure 3.jpg

Image With Caption
Paper #23.2 – “Ultra-Scaled MOCVD MoS2 MOSFETs with 42nm Contact Pitch and 250µA/µm Drain Current,” Q. Smets et al, Imec/KU Leuven
High Resolution Images
23.2 Figure 7.jpg
23.2 Figure 10.jpg

Image With Caption
Paper #26.1 – “Millimeter-Scale Thin-Film Batteries for Integrated High Energy-Density Storage,” S. Oukassi et al, CEA-Leti
High Resolution Images
26.1 Figure 2.jpg
26.1 Figure 18.jpg

Image With Caption
Paper #29.7 – “300mm Heterogeneous 3D Integration of Record Performance Layer Transfer Germanium PMOS with Silicon NMOS for Low-Power, High-Performance Logic Applications,” W. Rachmady et al, Intel
High Resolution Images
29.7 Figure 2.jpg
29.7 Figure 3.jpg
29.7 Figure 18.jpg

Image With Caption
Paper #30.1 – “Ultra-Low Power Physically Unclonable Function with Nonlinear Fixed-Resistance Crossbar Circuits,” M.R. Mahmoodi et al, UC-Santa Barbara
High Resolution Images
30.1 Figure 2.jpg
30.1 Figure 7.jpg

Image With Caption
Paper #33.1 – “A Silicon Photonics Technology for 400Gbit/s Applications,” F. Boeuf et al, STMicroelectronics/Univ. di Pavia
High Resolution Images
33.1 Figure 2.jpg
33.1 Figure 9.jpg
33.1 Figure 10.jpg
33.1 Figure 17.jpg

Image With Caption
Paper #36.7 – “5nm CMOS Production Technology Platform Featuring Full-Fledged EUV and High-Mobility Channel FinFETs with Densest 0.021µm2 SRAM Cells for Mobile SoC and High-Performance Computing Applications,” G. Yeap et al, TSMC
High Resolution Images
36.7 Figure a.jpg
36.7 Figure b.jpg
36.7 Figure c.jpg
36.7 Figure d.jpg
36.7 Figure e.jpg

Image With Caption
Paper #38.1 – “Optimal Design Methods to Transform 3D NAND Flash into a High-Density, High-Bandwidth and Low-Power Nonvolatile Computing-in-Memory (nvCIM) Accelerator for Deep-Learning Neural Networks,” H.T. Lue et al, Macronix
High Resolution Images
38.1 Figure 4.jpg
38.1 Figure 5.jpg
38.1 Figure 15.jpg

Image With Caption
Paper #39.5 – “Multiphysics Simulation & Design of Silicon Quantum Dot Qubit Devices,” F.A. Mohiyaddin, Imec/KU Leuven/ETH Zurich
High Resolution Images
39.5 Figure 1.jpg
39.5 Figure 17.jpg

ATTENDANCE AT IEDM IS COMPLIMENTARY FOR THE PRESS.
If you plan to attend, please let us know. Also, the conference organizers are planning to have a press luncheon at the beginning of the IEDM to discuss the most interesting papers and the major technology trends evident in this year’s program. We encourage journalists to attend it, and details will be provided in November.

Whether you would like to do a news story, conference preview or an in-depth exploration of a particular technology, please contact one of us for the additional information or interviews you may need.

Editor Contacts:
Gary Dagastine, co-Media Relations Director, at gdagastine@nycap.rr.com or by telephone at +1 518 785 2724
Chris Burke, co-Media Relations Director, at chris.burke@btbmarketing.com or by telephone at +1 919 872 8172

Registration/attendance questions:
Can be answered by the Conference Manager Phyllis Mahoney, at phyllism@widerkehr.com or by telephone at +1 240 449 6746. 19803 Laurel Valley Place, Montgomery Village, MD 20886 USA

ABOUT IEDM
IEEE International Electron Devices Meeting (IEDM) is the world’s pre-eminent forum for reporting technological breakthroughs in the areas of semiconductor and electron-device technology, design, manufacturing, physics, and modeling. IEDM is the flagship conference for nanometer-scale CMOS transistor technology, advanced memory, displays, sensors, MEMS devices, novel quantum and nano-scale devices and phenomenology, optoelectronics, devices for power and energy harvesting, high-speed devices, as well as process technology and device modeling and simulation. The conference scope not only encompasses devices in silicon, compound, and organic semiconductors, but also emerging material systems.

The IEEE Electron Devices Society is dedicated to promoting excellence in the field of electron devices, and sponsors the IEDM. Learn more at ieee-iedm.org.