IEDM

Session 3: Circuit Device Integration Advanced CMOS Technology Platform

Monday, December 15, 1:30 p.m.
Grand Ballroom A
Co-Chairs: Shigenobu Maeda, Samsung Electronics
Myunghee Na, IBM

1:35 p.m.
3.1 An Enhanced 16nm CMOS Technology Featuring 2nd Generation FinFET Transistors and Advanced
Cu/low-k Interconnect for Low Power and High Performance Applications, S.-Y. Wu, C.Y. Lin, M.C. Chiang, J.J. Liaw, J.Y. Cheng, S.H. Yang, S.Z. Chang, M. Liang, T. Miyashita, C.H. Tsai, C.H. Chang, V.S. Chang, Y.K. Wu, J.H.
Chen, H.F. Chen, S.Y. Chang, K.H. Pan, R.F. Tsui, C.H. Yao, K.C. Ting, T. Yamamoto, H.T. Huang, T.L. Lee, C.H. Lee,
W. Chang, H.M. Lee, C.C. Chen, T. Chang, R. Chen, Y.H. Chiu, M.H. Tsai, S.M. Jang, K.S. Chen, Y. Ku, Taiwan
Semiconductor Manufacturing Company

Advancing the state-of-the-art 16nm technology reported last year, an enhanced 16nm CMOS technology featuring the
2nd generation FinFET transistors and advanced Cu/low-k interconnect is presented. Core devices are re-optimized to
provide additional 15% speed boost or 30% power reduction. Device overdrive capability is also extended by 70mV
through reliability enhancement. Superior 128Mb HD SRAM Vccmin capability of 450mV is achieved with variability
reduction for the first time. Metal capacitance reduction by ~9% is realized with advanced interconnect scheme to enable
dynamic power saving.

2:00 p.m.
3.2 Analog Circuit and Device Interaction in High-Speed SerDes Design in 16nm FinFet Process, F. Zhong and A. Sinha, Avago Technology Inc.

SerDes, a critical component in communication systems, deals with data serialization, deserialization and channel
equalization up to 28Gb/s and beyond. Many SerDes were designed and fabricated in 250nm to 16nm CMOS technology
in past 15 years. Process technology and device characteristic impacts greatly the architecture, circuit topology, and
design merit of a SerDes. Several architecture choices, analog circuits, and techniques to mitigate undesired device
characteristic in 16nm FinFet were discussed in this paper. Taking advantage of deep sub-micron technology and
mitigating undesired device characteristic, like 16nm FinFet, 28Gb/s SerDes was developed and demonstrated desired
performance, power and die area.

2:25 p.m
3.3 16 nm FinFET High-k/Metal-gate 256-kbit 6T SRAM Macros with Wordline Overdriven Assist, M.
Yabuuchi, M. Morimoto, Y. Tsukamoto, S. Tanaka, K. Tanaka, M. Tanaka and K. Nii, Renesas Electronics Corporation
We demonstrate 16 nm FinFET High-k/Metal-gate SRAM macros with wordline (WL) overdriven read/write-assist
circuit. A test-chip measurement successfully confirms the improvement in minimum operating voltage (Vmin), standby
leakage current and access time, compared to the previous planar bulk CMOS. For instance, the proposed assist circuit
improves by 50 mV Vmin and over 1.5x read-access-time in 256-kbit SRAM macros. We also observed the read current
(Iread) dependencies against the length of fin diffusion, implying extra design guard-band to assure the operation margin.

2:50 p.m.
3.4 Single-P-Well SRAM Dynamic Characterization with Back-Bias Adjustment for Optimized Wide-VoltageRange SRAM Operation in 28nm UTBB FD-SOI, O. Thomas, B. Zimmer, S. Toh, L. Campiolini*, N. Planes*, R. Ranica*, P. Flatresse* and B. Nikolic, Berkeley Wireless Research Center, *STMicroelectronics
This paper demonstrates the 28nm ultra-thin body and buried oxide (UTBB) FD-SOI high-density (0.120µm²) single pwell
(SPW) bitcell architecture for the design of low-power wide voltage range systems enabled by back-bias adjustment.
The results from a 140kb programmable dynamic SRAM characterization test module provide both information about
location and cause of failures as well as power and performance by mimicking system operating conditions over a wide
supply voltage range. A 410mV minimum operating voltage and less than 310mV data retention voltage with less than
100fA/bitcell are measured. Improved bitcell read access time and write-ability through back-bias are demonstrated with
less than 5% of stand-by power overhead.

3:15 p.m.
3.5 Drain Extended MOS Device Design for Integrated RF PA in 28nm CMOS with Optimized FoM and ESD
Robustness, A. Gupta, M. Shrivastava*, M.S. Baghini, D.K. Sharma, A.N. Chandorkar, H. Gossner** and V.R. Rao,
Indian Institute of Technology Bombay, *Indian Insitute of Science Bangalore, **Intel Corp.
This paper explores drain extended MOS (DeMOS) device design guidelines for an area scaled, ESD robust integrated
radio frequency power amplifier (RFPA) for advanced system-on-chip applications in 28nm node CMOS. Simultaneous
improvement of device-circuit performance and ESD robustness is discussed for the first time. By device design
optimization a 45% increase in gain and 25% in power-added efficiency of RF PA at 1GHz, and 5× improvements in ESD
robustness are reported experimentally.

3:40 p.m.
3.6 Heterogeneously Integrated sub-40nm Low-power Epi-like Ge/Si Monolithic 3D-IC with Stacked SiGeC
Ambient Light Harvester, C.-H. Shen, J.-M. Shieh, T.-T. Wu, W.-H. Huang, G.-W. Huang, M.-F. Chang* and F.-L.
Yang**, National Nano Device Laboratories, *National Tsing Hua University, **Academia Sinica
For the first time, we report heterogeneously integrated sub-40nm epi-like Ge/Si monolithic 3D-IC with low-power
logic/NVM circuits and efficient photovoltaic energy harvester. Threshold voltage engineering and driving current
boosting technologies enable stackable Ge/Si UTB (<15nm) MOSFETs, CMOS inverter and SRAM
(SNM=270mV@0.7V) achieve low operation voltage. Stackable 1-T NVM with high speed (100ns) and low drivingvoltage
operation provide power-off storage while SRAM serve as power-on working memory. 100% aperture ratio
SiGeC ambient light energy harvester with maximum output power of 7mW/cm2 layered on the monolithic 3D-IC chip envisions a self-powered monolithic 3D-IC technology for advanced low-power wire-less sensor networks, wearable
devices, and devices for Internet of Things.

4:05 p.m.
3.7 A 14nm Logic Technology Featuring 2nd-Generation FinFET Transistors, Air-Gapped Interconnects, Self Aligned Double Patterning and a 0.0588m2 SRAM Cell Size (Late News), S. Natarajan, M. Agostinelli*, S. Akbar, M. Bost, A. Bowonder, V. Chikarmane, S. Chouksey, A. Dasgupta, K. Fischer, Q. Fu, T. Ghani, M. Giles**, S. Govindaraju, R. Grover, W. Han, D. Hanken, E. Haralson, M. Haran, M. Heckscher, R. Heussner, P. Jain, R. James, R. Jhaveri, I. Jin, H. Kam, E. Karl, C. Kenyon, M. Liu, Y. Luo, R. Mehandru**, S. Morarka**, L. Neiberg, P. Packan, A. Paliwal, C. Parker, P. Patel, R. Patel, C. Pelto, L. Pipes, P. Plekhanov, M. Prince, S. Rajamani, J. Sandford, B. Sell, S. Sivakumar, P. Smith, B. Song, K. Tone, T. Troeger, J. Wiedemer, M. Yang, K. Zhang

A 14nm logic technology using 2nd-generation FinFET transistors with a novel subfin doping technique, self-aligned
double patterning (SADP) for critical patterning layers, and air-gapped interconnects at performance-critical layers is
described. The transistors feature rectangular fins with 8nm fin width and 42nm fin height, 4th generation high-k metal
gate, and 6th generation strained silicon, resulting in the highest drive currents yet reported for 14nm technology. This
technology is in high-volume manufacturing.

4:20 p.m.
3.8 High Performance 14nm SOI FinFET CMOS Technology with 0.0174μm2 embedded DRAM and 15 Levels of Cu Metallization (Late News), C-H. Lin, B. Greene, S. Narasimha, J. Cai, A. Bryant, C. Radens, V. Narayanan, B. Linder, H. Ho, A. Aiyar, E. Alptekin, J-J. An, M. Aquilino, R. Bao, V. Basker, N. Breil, M. Brodsky, W. Chang, L.
Clevenger, D. Chidambarrao, C. Christiansen, D. Conklin, C. DeWan, H. Dong, L. Economikos, B. Engel, S. Fang, D.
Ferrer, A. Friedman, A. Gabor, F. Guarin, X. Guan, M. Hasanuzzaman, J. Hong, D. Hoyos, B. Jagannathan, S. Jain, S-J.
Jeng, J. Johnson, B. Kannan, Y. Ke, B. Khan, B. Kim, S. Koswatta, A. Kumar, T. Kwon, U. Kwon, L. Lanzerotti, H-K
Lee, W-H. Lee, A. Levesque, W. Li, Z. Li, W. Liu, S. Mahajan, K. McStay, H. Nayfeh, W. Nicoll, G. Northrop, A. Ogino,
C. Pei, S. Polvino, R. Ramachandran, Z. Ren, R. Robison, I. Saraf, V. Sardesai, S. Saudari, D. Schepis, C. Sheraw, S.
Siddiqui, L. Song, K. Stein, C. Tran, H. Utomo, R. Vega, G. Wang, H. Wang, W. Wang, X. Wang, D. Wehelle-Gamage,
E. Woodard, Y. Xu, Y. Yang, N. Zhan, K. Zhao, C. Zhu, K. Boyd, E. Engbrecht, K. Henson, E. Kaste, S. Krishnan, E.
Maciejewski, H. Shang, N. Zamdmer, R. Divakaruni, J. Rice, S. Stiffler, P. Agnello

We present a fully integrated 14nm CMOS technology featuring finFET architecture on an SOI substrate for a diverse set
of SoC applications including HP server microprocessors and LP ASICs. This SOI finFET architecture is integrated with
a 4th generation deep trench embedded DRAM to provide an ultra-dense (0.0174um2) memory solution for industry
leading ‘scale out’ processor design. A broad range of Vts is enabled on chip through a unique dual workfunction process
applied to both NFETs and PFETs. This enables simultaneous optimization of both lowVt (HP) and HiVt (LP) devices
without reliance on problematic approaches like heavy doping or Lgate modulation to create Vt differentiation. The SOI
finFET’s excellent subthreshold behavior allows gate length scaling to the sub 20nm regime and superior low Vdd
operation. This leads to a substantial (>35%) performance gain for Vdd ~0.8V compared to the HP 22nm planar
predecessor technology. At the same time, the exceptional FE/BE reliability enables high Vdd (>1.1V) operation essential
to the high single thread performance for processors intended for ‘scale-up’ enterprise systems. A hierarchical BEOL with
15 levels of copper interconnect delivers both high performance wire-ability as well as effective power supply and clock
distribution for very large >600mm2 SoCs.

4:35 p.m.
3.9
A 55nm Triple Gate Oxide 9 Metal Layers SiGe BiCMOS Technology Featuring 320 GHz fT/370 GHx fMAX HBT and High-Q Millimeter-Wave Passives (Late News), P. Chevalier, G. Avenier, G. Ribes, A. Montagne, E. Chanderle, D. Celi, N. Derrier, C. Deglise, C. Durand, T. Quemerais, M. Buczko, D. Gloria, O. Robin, S. Petitdidier, Y. Campidelli, F. Abbate, M. Gros-Jean, I. Berthier, J.D. Chapon, F. Leverd, C. Jenny, C. Richard, O. Gourhant, C. De-Buttet, R.
Beneyton, P. Maury, S. Joblot, L. Favennec, M. Guillermet, P. Brun, K. Courouble, K. Haxaire, G. Imbert, E. Gourvest, J.
Cossalter, O. Saxod, C. Tavemier, F. Foussadier, B. Ramadout, R. Bianchini, C. Julien, D. Ney, J. Rosa, S. Haendler, Y.
Carminati, B. Borot

This paper presents the first 55 nm SiGe BiCMOS technology developed on a 300 mm wafer line in STMicroelectronics. The technology features Low Power (LP) and General Purpose (GP) CMOS devices and 0.45 µm² 6T-SRAM bit cell. High Speed (HS) HBT exhibits 320 GHz fT and 370 GHz fMAX associated with a CML ring oscillator gate delay D of 2.34 ps. Transmission lines, capacitors, high-Q varactors and inductors dedicated to millimeter-wave applications are also available.