IEDM

Session 9: Process and Manufacturing Technology 3D Integration and BEOL

Tuesday, December 6, 9:00 a.m.
Grand Ballroom A
Co-Chairs: Lucille Arnaud, CEA Leti
Takahiro Kouno, Socionext

9:05 AM
9.1 Footprint-efficient and Power-saving Monolithic IoT 3D+ IC Constructed by BEOL-compatible sub-10nm High Aspect Ratio (AR>7) Single-grained Si FinFETs with Record High Ion of 0.38 mA/µm and Steep-swing of 65 mV/dec. and Ion/Ioff Ratio of 8, C.-C. Yang, J.-M. Shieh, T.-Y. Hsieh, W.-H. Huang, H.-H. Wang, C.-H. Shen, F.-K. Hsueh, P.-Y. Hsieh, M.-C. Wu* and W.-K. Yeh, National Nano Device Laboratories, *National Tsing Hua University

A footprint-efficient and power-saving BEOL compatible 3D+IC carrying monolithic 3D stackable FinFETs (3D+ FinFETs) and W interconnect were demonstrated by low thermal budget laser spike anneal technology (Tsub<400oC) and body-nano-planarizing processes. The narrow single-grained Si fin structure with ultra-low defect surface were fabricated by anisotropic ICP plasma etching and surface modification processes. The thus fabricated sub-10 nm and high aspect ratio (HFin/WFin>7) 3D+ FinFETs exhibit steep subthreshold swing (S.S.~65mV/dec.), record high driving current (Ion per WEff (WEff=2HFin+WFin): 386 uA/um (n-type) and 352uA/um (p-type)), and high Ion/Ioff (>107), envisioning next generation low-cost heterogeneously integrated IoTs and wearable electronics.

9:30 AM
9.2 An Advanced 3D/2.5D Integration Packaging Approach Using Double-Self-Assembly Method with Complex Topography, and Micropin-Fin Heat Sink Interposer for Pressure Sensing System, Y.-C. Hu, C.-P. Lin*, H.-C. Chang, Y.-T. Yang, C.-S. Chen* and K.-N. Chen, National Chiao Tung University, *National Applied Research Laboratories

To cater complex topography sensors and circuit chips for smart lifestyle applications using IoT, we develop a novel efficient double-self-assembly packaging approach by 3D/2.5D heterogeneous integration. This technology is able to integrate various kinds of processed chips, especially with uneven surface and bottom topography. With liquid surface tension, complex topography chips can be handled and self-aligned on precise locations. Double-self-assembly approach demonstrates temporary bonding on carrier wafer and self- aligned permanent bonding in a pressure sensing system packaging. The optimized volume of liquid to use on various complex topography shapes and areas are investigated, while Cu/In low temperature metal bonding and self-assembly approach for high I/O density and low bonding resistance are demonstrated. Excellent electrical characteristics and mechanical strength of show the feasibility of the double-self-assembly approach on complex topography surface chips packaging applications.

9:55 AM
9.3 Interconnect Scaling: Challenges and Opportunities (Invited), R. Brain, Intel Corp.

Transistor and interconnect pitch scaling has been used successfully for greater than 40 years to drive significant density and performance benefits in integrated circuits. Transistor performance has continued to improve due to pitch scaling combined with other process enhancements. Interconnects represent a much larger portion of the overall delay and cost of integrated circuits today than in the past. This paper reviews the relative comparison of interconnect and transistor scaling and key interconnect scaling challenges, and it highlights the transistor/interconnect co-optimization that is needed to create high performance and high yielding interconnects sufficient for today’s ultra-large scale integration (ULSI) needs, and reviews future trends.

10:20 AM
9.4 CMOS Compatible MIM Decoupling Capacitor with Reliable Sub-nm EOT High-k Stacks for the 7 nm Node and Beyond, T. Ando, E. Cartier, P. Jamison*, A. Pyzyna, S. Kim, J. Bruley, K. Chung*, H. Shobha*, I. Estrada-Raygoza*, H. Tang*, S. Kanakasabapathy*, T. Spooner*, L. Clevenger*, G. Bonilla*, H. Jagannathan*, V. Narayanan, IBM T. J. Watson Research Center, *IBM Research @ Albany Nanotech

We demonstrate a record-low EOT of 0.8 nm for a BEOL MIM decoupling capacitor. We identify that electrical symmetry for opposite bias polarities is a key for multi-plate MIM capacitors. Our novel high-k stack with aggressively scaled EOT and ideal symmetry enables further capacitance enhancements for the 7 nm node and beyond.

10:45 AM
9.5 BEOL Compatible Graphene/Cu with Improved Electromigration Lifetime for Future Interconnects, L. Li, Z. Zhu*, T. Wang**, J. A. Currivan-Incorvia, A. Yoon* and H.-S. P. Wong, Stanford University, *Lam Research Corp., **Zhejiang University

We demonstrate a method to grow graphene directly on patterned Cu wires below 400 °C, within the thermal budget of back-end-of line processes (BEOL). The process flow is compatible with direct etched Cu processes for advanced interconnects technology. The graphene/Cu composite exhibits 2× lower resistivity, 1.4× higher breakdown current density and 40× longer electromigration (EM) lifetime than as-deposited Cu. The electromigration performance of graphene/Cu is 10× better than 2 nm CoWP on Cu, and is comparable to the industry-standard 3 nm CoWP capping layer. DFT calculated reveal that the binding between the pristine in-situ grown graphene and Cu makes the Cu atom more resilient to external forces.

11:10 AM
9.6 Vertical Channel Devices Enabled by Through Silicon Vias (TSV) Technologies, C. Kothandaraman, S. Rosenblatt, J. Safran*, P. Oldiges, P. Kulkarni-Kerber, J. Xumalo*, W. Landers, J. Liu, J. Oakley, S. Butt*, T. Graves-Abe*, N. Robson*, M. Farooq*, D. Berger* and S. Iyer**, IBM T.J. Watson Research Center, *Global Foundries, **UCLA

Novel device structures with vertical channels gated by TSV’s are demonstrated. The unique device structure is realized in a standard TSV process flow, without new material systems or processes. They can be used for both characterizing the TSV process as well as enable new functions.