Session 5: Nano Device Technology 1D and 2D Devices

Monday, December 5, 1:30 p.m.
Continental Ballroom 5
Co-Chairs: Heike Riel, IBM Research
Deji Akinwande, University of Austin, Texas

1:35 PM
5.1 Carbon Nanotube Complementary Logic with Low-Temperature Processed End-Bonded Metal Contacts, J. Tang, Q. Cao, D. Farmer, G. Tulevski and S.-J. Han, IBM T.J. Watson Research Center

We demonstrate a new form of end-bonded contacts to CNTs by carbon dissolution into metal contacts with high carbon solubility (e.g., Ni, Co), requiring only low-temperature annealing. We further fabricate complementary logic using end-boned Ni contacts, where stable NFETs are converted from PFETs using Al2O3 as n-type doping layer.

2:00 PM
5.2 First Demonstration of a Wrap-Gated CNT-FET with Vertically-Suspended Channels, D. Lee, B.-H. Lee, J. Yoon*, B. Choi*, J.-Y. Park, D.-C. Ahn, C.-K. Kim, B.-W. Hwang, S.-B. Jeon, H. J. Ahn, M.-L. Seol**, M.-H. Kang***, B. J. Cho, S.-J. Choi,* Y.-K. Choi, KAIST (Korea Advanced Institute of Science and Technology), *Kookmin University, **NASA, ***National Nanofab Center

Fully wrap-gated carbon nanotube transistors with vertically suspended semiconducting single-walled CNTs, purified up to 99.9%, are demonstrated for the first time. Without a sacrifice of scalability, remarkably enhanced gate controllability and charge transport capabilities were achieved due to the geometrical advantage of the gate-all-around structure with multiple channels. The VS channels were formed with the aid of a silicon-processed vertically integrated nanowire frame, offering high completeness and compatibility with silicon processes.

2:25 PM
5.3 Record Low Metal – (CVD) Graphene Contact Resistance Using Atomic Orbital Overlap Engineering, A. Meersha, H. Variar, K. Bhardwaj, A. Mishra, S. Raghavan, N. Bhat and M. Shrivastava, Indian Institute of Science, Bangalore

Different techniques to engineer atomic orbital overlap are proposed to improve metal – graphene contact. Fundamental insight into the orbital overlap engineering has resulted in record low contact resistance at room temperature. This has pushed graphene FET to its intrinsic limits with capability to scale, leading to record high transistor performance.

2:50 PM
5.4 First-principles Simulations of 2-D Semiconductor Devices: Mobility, I-V Characteristics, and Contact Resistance (Invited), M. Luisier, A. Szabo, C. Stieger, C. Klinkert, S. Brück, A. Jain and L. Novotny, ETH Zurich

We report in this paper ab-initio quantum transport simulations of different types of single-layer 2-D semiconductors: transition metal and group IV dichalcogenides in the 2H or 1T phase as well as black phosphorus. The electron and hole phonon-limited mobilities of eight selected 2-D crystals are first analyzed before using these materials as n- or p-type channels of ultra-scaled single-gate transistors, computing their I-V characteristics in the presence of electron-phonon scattering, and comparing them to each other. Finally, the properties of metal-MoS2 contacts are investigated. It is revealed that the current tends to flow at the edge of the metal layer before entering the semiconductor, thus limiting the injection efficiency.

3:15 PM
5.5 Few-Layer Black Phosporous PMOSFETs with BN/Al2O3 Bilayer Gate Dielectric: Achieving Ion=850μA/μm, gm=340μS/μm, and Rc=0.58kΩμm, L. Yang, G. Qiu, M. Si, A. Charnas, C.A. Milligan, D. Zemlyanov, H. Zhou, Y. Du, Y.-M. Li*, W. Tsai*, Q. Paduano**, M. Snure** and P. Ye, Purdue University, *TSMC, **AFRL

In this paper, high-performance few-layer black phosphorus (BP) PMOSFETs have been demonstrated by using MOCVD BN and ALD Al2O3 as the top-gate dielectric as well as the passivation layer. Highest Ion of 850μA/μm (Vds = -1.8V) and gm of 340μS/μm (Vds = -0.8V) have been achieved with the 200nm chancel length (Lch) devices. Record low contact resistance (Rc) of 0.58kOhmμm has been obtained on BP transistors by contact engineering. The gate leakage of the BN/Al2O3 bilayer gate dielectric is less than 10-12A/μm2 (Vg = -1V) with an EOT of 3nm. SS and hysteresis voltage as low as 70mV/dec and 0.1V have been achieved, indicating a high quality interface between BP and BN.

3:40 PM
5.6 Approaching Ballistic Transport in Monolayer MoS2 Transistors with Self-Aligned 10 nm Top Gates, C. English, K. Smithe, R. Xu and E. Pop, Stanford University

We present 10 nm self-aligned top-gated transistors based on monolayer MoS2. We achieve record saturation current (>400 uA/um), excellent sub-threshold slope and EOT. Combining modeling and measurements, we examine diffusive vs. ballistic transport and suggest a route to advance MoS2 transistors closer to the ballistic limit.

4:05 PM
5.7 High-Yield Large Area MoS2 Technology: Material, Device and Circuits Co-optimization, L. Yu, D. El-Damak, U. Radhakrishna, A. Zubair, D. Piedra, X. Ling, Y. Lin, Y. Zhang, Y.-H. Lee*, D. Antoniadis, J. Kong, A. Chandrakasan, T. Palacios, Massachusetts Institute of Technology, *National Tsing-Hua University;

Two-dimensional electronics based on single-layer (SL) MoS2 offers significant advantages for realizing large-scale flexible systems owing to the ultrathin nature, good transport properties and stable crystalline structure of MoS2. However, the reported devices and circuits based on this material have low yield because of various variation sources inherent to the growth and fabrication technology. In this work, we develop a variation-aware design flow and yield model to evaluate the MoS2 technology and provide a guideline for the co-optimization of the material, devices and circuits. Test chips with various inverters and basic logic gates (such as NAND and XOR) are fabricated as demonstration of the close- to-unit yield of the proposed technology platform.

4:30 PM
5.8 Quantitative Evaluation of Energy Distribution of Interface Trap Density at MoS2 MOS Interfaces by the Terman Method, M. Takenaka, Y. Ozawa, J. Han and S. Takagi, The University of Tokyo

By using Terman method, we reveal MoS2 MOS interfaces exhibit Dit peak of approximately 1E13 cm-2eV-1 related to sulfur vacancies in MoS2 with nearly constant Dit of 1E12 cm-2eV-1. In conjunction with subthreshold swing analyses in MoS2 MOSFETs, we successfully grasp energy distribution of Dit at native MoS2 MOS interfaces.