IEDM

Session 4: Memory Technology RRAM, PRAM and Applications

Monday, December 5, 1:30 p.m.
Continental Ballroom 4
Co-Chairs: Fabio Pellizer, Micron
John Paul Strachan, Hewlett Packard Labs

1:35 PM
4.1 Towards Ultimate Scaling Limits of Phase-Change Memory (Invited), F. Xiong, E. Yalon, A. Behnam*, C.M. Neumann, K.L. Grosse*, S. Deshmukh and Eric Pop, Stanford University, *University of Illinois Urbana-Champaign

Data storage based on a reversible material phase transition (e.g. amorphous to crystalline) has been studied for nearly five decades. Yet, it was only during the past five years that some phase-change memory technolo-gies (e.g. GeSbTe) have been approaching the physical scaling limits of the smallest possible memory cell. Here we review recent results from our group and others, which have achieved sub-10 nm scale PCM with switching energy approaching single femtojoules per bit. Fundamental limits could be as low as single attojoules per cubic nanometer of the memory material, although approaching such limits in practice appears strongly limited by electrical and thermal parasitics, i.e. contacts and interfaces.

2:00 PM
4.2 ALD-based Confined PCM with a Metallic Liner toward Unlimited Endurance, W. Kim, M. BrightSky, T. Masuda*, N. Sosa, S. Kim, R. Bruce, F. Carta, G. Fraczak, H.-Y. Cheng**, A. Ray, Y. Zhu, H.-L. Lung**, K. Suu*, and C. Lam, IBM T.J. Watson Research, *ULVAC, Inc., **Macronix

We present for the first time in-depth analysis of the outstanding endurance characteristics of an ALD-based confined phase change memory with a thin metallic liner. This confined PCM with a metallic liner exhibits a new record endurance (2e12 cycles) and is found to be immune to classic endurance failure mechanisms.

2:25 PM
4.3 SiOx-based Resistive Switching Memory (RRAM) for Crossbar Storage/select Elements with High on/off Ratio, A. Bricalli, E. Ambrosi, M. Laudato, M. Maestro*, R. Rodriguez* and D. Ielmini, Politecnico di Milano, *Universitat Autònoma de Barcelona

Resistive switching memory (RRAM) is among the most promising technologies for storage class memory (SCM) and embedded nonvolatile memory (eNVM). Feasibility of RRAM as SCM and/or embedded memory requires large on/off ratio, good endurance, high retention, and the availability of a robust select element for crossbar array integration. This work presents Ti/SiOx RRAM with high on/off ratio (>104), good endurance (>107), high uniformity and strong retention (260°C for 1 hour), thanks to the high SiOx band gap. Ag/SiOx devices show volatile switching with high on/off ratio (> 107) and bidirectional operation applicable to select devices in crossbar arrays.

2:50 PM
4.4 Forming-Free Metal-Oxide ReRAM by Oxygen Ion Implantation Process, W. Kim, A. Hardtdegen, C. Rodenbücher, S. Menzel, D. Wouters*, S. Hoffmann-Eifert, D. Buca, R. Waser* and V. Rana, Forschungszentrum Jülich GmbH, *RHTH Aachen University

We propose a new method for obtaining formingfree ReRAM devices by oxygen ion implantation (O2 IIP) in the metal oxide film during the device fabrication process. By tuning the implantation dose, as- fabricated devices can be transformed into the ON state. Subsequent standard RESET and SET switching cycles reveal that the forming-free devices switch in a similar way to reference (formed) devices. The devices also show good ROFF/RON>200, retention (1E4 sec@125ºC) and endurance reliability (1E6 cycles), showing the absence of any device degradation caused by the O2 IIP process. This method is applied on both (PVD) Ta2O5 and (ALD) HfO2 nanoscale ReRAM devices, demonstrating the versatile applications of the technique.

3:15 PM
4.5 Understanding RRAM Endurance, Retention and Window Margin Margin Trade-off using Experimental Results and Simulations, C. Nail, G. Molas, P. Blaise, G. Piccolboni, B. Sklenard, C. Cagli, M. Bernard, A. Roule, M. Azzaz, E. Vianello, C. Carabasse, R. Berthier, D. Cooper, T. Magis, C. Pelissier, G. Ghibaudo*,C. Vallée***, B. De Salvo, L. Perniola, D. Bedeau** and O. Mosendz**, CEA/LETI, *IMEP/LAHC/CNRS, **WD San Jose Research Center, ***LTM/CNRS

In this paper we clarify for the first time the correlation between endurance, window margin and retention of Resistive RAM. To this aim, various classes of RRAM (OXRAM and CBRAM) are investigated, showing high window margin up to 1010 cycles or high 300°C retention. From first principle calculations, we analyze the conducting filament composition for the various RRAM technologies, and extract the key filament features. We then propose an analytical model to calculate the dependence between endurance, window margin and retention, linking material parameters to memory characteristics.

3:40 PM
4.6 Statistical Investigation of the Impact of Program History and Oxide-metal Interface on OxRRAM Retention, C.-Y. Chen, A. Fantini, R. Degraeve, A. Redolfi, G.Groeseneken, L. Goux and G. Kar, imec

Statistically investigation on weak retention bits in OxRRAM devices is performed. For a same cell, retention is affected by pulse duration, pre-Write pulse-pattern, and delay between pulses. Together with material engineering and programming optimization, data stability improvement via tuning of oxygen chemical potential profile along the conductive filament is demonstrated.

4:05 PM
4.7 Fundamental Variability Limits of Filament-based RRAM, A. Grossi, E. Nowak, C. Zambelli*, C. Pellissier, S. Bernasconi, G. Cibrario, K. El Hajjam, R. Crochemore, J.-F. Nodin, P. Olivo* and L. Perniola, CEA LETI, *Università degli Studi di Ferrara

While Resistive RAM (RRAM) are seen as an alternative to NAND Flash, their variability and cycling understanding remain a major roadblock. Extensive characterizations of multi-kbits RRAM arrays during Forming, Set, Reset and cycling operations are presented allowing the quantification of the intrinsic variability factors. As a result, the fundamental variability limits of filament-based RRAM in the full resistance range are identified.

4:30 PM
4.8 True Random Number Generator using Current Difference based on a Fractional Stochastic Model in 40-nm Embedded ReRAM, Z. Wei, Y. Kato, S. Ogasahara, Y. Yoshimoto, K. Kawai, Y. Ikeda, K. Eriguchi*, K. Ohmori** and S. Yoneda, Panasonic Semiconductor Solutions, *Kyoto University, **University of Tsukuba

We show a robust 40-nm ReRAM true random number generator without extra chip area. True random is guaranteed by current difference in 1/f noise generated by Brownian motion, tested with fractional SDE model. Designed generator circuit passed all NIST SP800-22 tests, achieved 32 Mbps throughput with 0.04 nJ/bit power consumption.