IEDM

Session 35: Circuit Device Interaction 3D Systems, Enabling Technologies and Characterizations

Wednesday, December 7, 1:30 p.m.
Continental Ballroom 6
Co-Chairs: Anne-Johan Annema, University of Twente
Susan Wu, Xilinx Inc.

1:35 PM
35.1 New Perspectives for Multicore Architectures using Advanced Technologies (Invited), F. Clermidy, P. Vivet, D. Dutoit, Y. Thonnart, J.-L. Gonzales, J.-P. Noël, B. Giraud, A. Lévisse, O. Billoint and S. Thuriès, University Grenoble Alpes, CEA-LETI

Impact of advanced technologies on the design and structure of multicore architectures is presented in this paper. More specifically, the power consumption and design complexity walls are examined leading to a “conquer-and-divide” strategy based on multicore partitioning and specialization. We then show how 3D stacking, Monolithic 3D integration and BEOL NVM can be associated to build new, simplified and power- efficient multicore.

2:00 PM
35.2 Ultra-Low-Resistance 3D InFO Inductors for Integrated Voltage Regulator Applications, C.-L. Chen, Y.-C. Hsu, J.-S. Hsieh, C.-H. Tsai, V. Chang, A. Roth, E. Soenen, C.-T. Wang and D. Yu, Taiwan Semiconductor Manufacturing Company, Ltd.

A novel 3D InFO inductor is developed to integrate with TSMC 16nm FinFET devices for high efficiency integrated voltage regulator. The InFO technology provides the ultra-low-resistance inductor (2.14 nH and 3.2 mOhm) and PDN (1.1 mOhm) concurrently for the IVR system design to achieve a peak power efficiency of 93%.

2:25 PM
35.3 High-Q Magnetic Inductors for High Efficiency On-Chip Power Conversion, N. Wang, B. Doris, A. B. Shehata, E. O’ Sullivan, S. Rossnagel, S. Brown, L. Gignac, J. Ott,. Massouras, L. Romankiw and H. Deligianni, IBM T. J. Watson Research Center

We experimentally demonstrate high performance magnetic inductors with Q as high as 17 in the frequency range of 50-250 MHz. These inductors meet target requirements for >90% efficient on-chip power converters. Physics-based models were used to understand magnetic losses, design novel magnetic stacks and innovative processes to achieve high Q.

2:50 PM
35.4 ESD Diodes in a Bulk Si Gate-All-Around Vertically Stacked Horizontal Nanowire Technology, S.-H. Chen, G. Hellings, M. Scholz, D. Linten, H. Mertens, R. Ritzenthaler, R. Boschke*, G. Groeseneken* and N. Horiguchi, imec, *KU Leuven

A Gate-All-Around (GAA) nanowire (NW) device is a candidate for sub-10nm bulk Si CMOS. The impact of the new architecture and its process options on intrinsic ESD performance needs to be studied. The measurement results and TCAD simulations prove that the ESD performance in bulk GAA NW based diodes is maintained in comparison to bulk FinFET diodes.

3:15 PM
35.5 Characterization of PVT Variation & Aging Induced Hold Time Margins of Flip-Flop Arrays at NTV in 22nm Tri-Gate CMOS, C. Augustine, C. Tokunaga, A. Malavasi, A. Raychowdhury*, M. Khellah, J. Tschanz and V. De, Intel Corporation, *Georgia Institute of Technology

With increasing process variation in scaled technology nodes, critical circuits are impacted which leads to performance loss/yield. We study min-delay in flip-flops in 22nm tri-gate CMOS and demonstrate through novel test-structures the impact of hold-time fluctuations across process/temperatures/voltage/aging conditions. This will guide design and process targets for min-delay failure mitigation.

3:40 PM
35.6 Thermal Resistance Modeling of Back-end Interconnect and Intrinsic FinFETs, and Transient Simulation of Inverters with Capacitive Loading Effects, J.-Y. Yan, S.-R. Jan, Y.-J. Peng, H. H. Lin*, W. K. Wan*, Y.-H. Huang*, B. Hung*, K.-T. Chan*, M. Huang*, M.-T. Yang* and C. W. Liu, National Taiwan University, *MediaTek Inc.

The intrinsic thermal resistances of 14nm FinFETs (Rth0, Device) are extracted with face-up and face-down configurations. Since the free convection of air has a large thermal resistance, the heat flow direction affects Rth0, Device. The volume of hot spot affects the cooling time. In an inverter, Tmax and the high temperature duration can be controlled by the current and output capacitive loading of the inverter. The residual temperature in the channel and the temperatures of M1 layer are found too low to reflect the real device temperature.