IEDM

Session 30: Modeling and Simulation Steep Slope Devices and Nanowires

Wednesday, December 7, 9:00 a.m.
Continental Ballroom 7-9
Co-Chairs: Debdeep Jena, Cornell University
Geert Eneman, IMEC

9:05 AM
30.1 Scaling Perspective for III-V Broken Gap Nanowire TFETs: An Atomistic Study using a Fast Tight-binding Mode-space NEGF Model, A. Afzalian, M. Passlack and Y.-C. Yeo, TSMC

We report an in-depth atomistic study of the scaling potential of III-V GAA nanowire heterojunction TFET using an innovative tight-binding mode space technique with large speedup (up to 250×). n- and pTFET performance is best above 20 nm gate length and features a gain of 58× over a Si MOSFET.

9:30 AM
30.2 A Tunnel FET Design for High-Current, 120 mV Operation, P. Long, J. Huang, M. Povolotskyi, D. Verreck*, J. Charles, T. Kubis, G. Klimeck, B. Calhoun** and M. Rodwell***, Purdue University, *IMEC, KU Leuven, **University of Virginia, ***University of California, Santa Barbara

We report simulations of logic transistor operation at supply voltages VDD between 0.08- 0.18V. Tunnel FETs (TFETs) can operate at low voltage with low off-currents IOFF , but on- currents ION are greatly reduced by low tunneling probability. The minimum feasible VDD is constrained not only by the transistor subthreshold swing (SS) given a target ION/IOFF ratio, but also by the reduction of the drain current as the drain Fermi level approaches the channel conduction-band energy. This output conductance reduces the TFET voltage gain and impairs the logic gate noise margin; increasing the TFET threshold voltage Vth increases the noise margin while reducing both ION and IOFF. In ballistic simulations with 10-3A/m IOFF, triple- heterojunction tunnel FETs (3HJ-TFETs) show >50% tunneling probability and a high 265A/m ION at VDD= 0.18V and 195A/m at VDD=0.12V. In simulations with an optical deformation constant (proportional to scattering strength) of 220meV/nm, consistent with =1.1×105 cm2V 1s-1, reduces ION by 31% given fixed IOFF and VDD. In ballistic simulations, increasing Vth by 0.02V above that required for 10-3A/m IOFF, a noise margin of 24% of VDD is obtained at VDD=0.12V.

9:55 AM
30.3 Effect of Band-Tails on the Subthreshold Performance of 2D Tunnel-FETs, H. Zhang, W. Cao, J. Kang and K. Banerjee, University of California, Santa Barbara

Rigorous analysis of band-tails in 2D semiconductors is presented for the first time. Photoluminescence measurements, analytical modeling, and first-principle calculations, are employed to unveil the unique advantages of these materials, especially in 2D-2D lateral heterostructures, in terms of band-edge smearing and its fundamental role in determining the subthreshold performance of 2D tunnel-FETs.

10:20 AM
30.4 Multi-barrier Inter-layer Tunnel Field-Effect Transistor, N. Prasad, X. Mou, L. Register and S. Banerjee, University of Texas at Austin

Resonant tunneling characteristics of the inter-layer tunnel field-effect transistor (ITFET) can be made sharper by the use of multiple tunnel barrier layers within a “mITFET” variation. NEGF simulations are used to obtain the resonance characteristics. Circuit simulations illustrate how the sharper resonance can lead to lower operating voltages and power.

10:45 AM
30.5 Compact Models of Negative-Capacitance FinFETs: Lumped and Distributed Charge Models, J. Duarte, S. Khandelwal, A. Khan, Y.-K. Lin, H.-L. Chang, S. Salahuddin and C. Hu, University of California, Berkeley

This work presents insights into the device physics and behaviors of ferroelectric based negative capacitance FinFETs (NC-FinFETs) by proposing lumped and distributed compact models for its simulation. NC-FinFET may have a floating metal between ferroelectric (FE) and the dielectric layers and the lumped charge model represents such a device. For a NC-FinFET without a floating metal, the distributed charge model should be used and at each point in the channel the ferroelectric layer will impact the local channel charge. This distributed effect has important implications on device characteristics as shown in this paper. The proposed compact models have been implemented in circuit simulators for exploring circuits based on NC-FinFET technology.

11:10 AM
30.6 Performance Projection of III-V Ultra-Thin-Body, FinFET, and Nanowire MOSFETs for two Next-Generation Technology Nodes, M. Rau, E. Caruso*, D. Lizzit*, P. Palestri*, D. Esseni*, L. Selmi*, A. Schenk and M. Luisier, ETH Zürich, *DIEGM, Universitá degli studi di Udine

The competitiveness of III-V compounds for next-generation high-performance logic switches at gate lengths 15 and 10.4 nm is confirmed using state-of-the art simulation tools. The gate-all-around nanowire architecture emerges as the only viable architecture worth scaling below 10.4 nm. III-V channels are found to significantly outperform their silicon counterparts at these nodes. The effects of series resistance combined with traps, surface roughness, alloy and electron-phonon scattering are found to deteriorate the ON-current by 50-60%.

11:35 AM
30.7 Vertically Stacked Nanowire MOSFETS for Sub-10 nm Nodes: Advanced Topography, Device, Variability, and Reliability Simulations, M. Karner, O. Baumgartner, Z. Stanojević, F. Schanovsky, G. Strof, C. Kernstock, HW. Karner, G. Rzepa* and T. Grasser*, Global TCAD Solutions GmbH, *TU Wien

Using our novel TCAD approach with advanced topology simulation, physical transport models for device performance, time-zero variability, and BTI device degradation modeling, we point out critical improvements required for the stacked NW-FET to surpass current FinFET technology for sub-10nm nodes.