IEDM

Session 28: Circuit and Device Interaction Technology Elements for 5nm Logic Platform and Advanced Automotive/IoT Applications

Wednesday, December 7, 9:00 a.m.
Continental Ballroom 5
Co-Chairs: Kang-ill Seo, Samsung Electronics
Koji Nii, Renesas Electronics

9:05 AM
28.1 A Novel Tensile Si (n) and Compressive SiGe (p) Dual-channel CMOS FinFET Co-integration Scheme for 5nm Logic Applications and Beyond, D. Bae, G. Bae, K. Bhuwalka, S.-H. Lee, M.-G. Song, T.-S. Jeon, C. Kim, W. Kim, J. Park, S. Kim, U. Kwon, J. Jeon, L.-J. Nam, S. Lee, S. Lian, K. Seo, S.-G. Lee, J. H. Park, Y.-C. Heo, M. S. Rodder, J. A. Kittle, Y. Kim, K. Hwang, D.-W. Kim, M.-S. Liang and ES Jung, Samsung Electronics

A novel tensile Si (tSi) and compressive SiGe (cSiGe) dual-channel FinFET CMOS co-integration scheme, aimed at logic applications for the 5nm technology node and beyond, is demonstrated for the first time, showing electrical performance benefits and excellent co-integration feasibility. A Strain-Relaxed SiGe Buffer (SRB) layer is introduced as buried stressor and successfully transfers up to ~1 GPa uniaxial tensile and compressive stress to the Si/SiGe n-/p-channels. As a result, both tSi and cSiGe devices show a 40% and 10% electron and hole mobility gain over unstrained Si, respectively. A common gate stack solution including a common interfacial layer (IL), HK, and metal gate for both n- and pFET is successfully developed. A gate stack process margin for the 5nm logic technology node is secured with low interface trap density (Dit) and threshold voltage (Vt) target for both the Si and SiGe devices, by skipping the dual Work Function Metal (WFM) processing and by simplifying the multi-Vth process module. Lastly, reliability investigation shows that tSi and cSiGe, employing the newly developed common gate stack scheme, possess superior reliability characteristics compared with those of equivalent Si devices.

9:30 AM
28.2 Extreme Scaling Enabled by 5 Tracks Cells: Holistic Design-device Co-optimization for FinFETs and Lateral Nanowires, M. Garcia Bardon, Y. Sherazi, P. Schuddinck, D. Jang, D. Yakimets, P. Debacker, R. Baert, H. Mertens, M. Badaroglu, A. Mocuta, N. Horiguchi, D. Mocuta, P. Raghavan, J. Ryckaert, A. Spessot, D. Verkest and A. Steegen, imec

By optimizing design rules, layout, devices and parasitics, we show how 5 Tracks standard cells with one fin can be enabled. This reduces area by 16% without pitch scaling and provides 34% energy gain. The loss in speed of 15% can be recovered by different front-end solutions. Air gap spacers are the most efficient booster and provide an extra 16% gain in energy. Lateral Nanowires can compete in speed with FinFETs with an extra energy gain of 12% if tight vertical pitch of 10 nm between wires can be achieved.

9:55 AM
28.3 32-bit Processor Core at 5-nm Technology: Analysis of Transistor and Interconnect Impact on VLSI System Performance, C.-S. Lee, B. Cline*, S. Sinha*, G. Yeric* and H.-S. P. Wong, Stanford University, *ARM Inc.

32-bit processor core is implemented at 5-nm design rules to study transistor and interconnect technology and their impact on system performance. 2D-material-based FETs can theoretically achieve 2x better system performance compared to Si FinFET for the same contact resistivity; wire does not dominate at 5-nm node thanks to routing optimization.

10:20 AM
28.4 New Insights into the Near-Threshold Design in Nanoscale FinFET Technology for Sub-0.2V Applications, X. Jiang, S. Guo, R. Wang, Y. Wang, X. Wang*, B. Cheng*, A. Asenov* and R. Huang, Peking University, *Synopsys

Energy consumption has become the major concern of the IC industry. As a result, near-threshold-voltage (NTV) design has attracted a lot of attention for its superiority in energy efficiency. However, NTV design is faced with the key challenge—variability, especially for FinFET technology where device electrical FoMs are found to be strongly correlated. In this paper, new methodology of NTV design optimization for FinFET is proposed for the first time, and demonstrated based on silicon data. Significant improvements are achieved in the following three aspects: (1) Our newly proposed predictive compact variability models in all-region are accurately calibrated with experimental data, using a simple characterization method; (2) A new efficient approach for logic design space optimization is proposed based on a set of elaborately selected subthreshold FoMs, and the impacts of variation on energy efficiency, delay variation and failure probability are thoroughly investigated; (3) The conventional gate sizing method is also ameliorated specifically for FinFET NTV design. Based on silicon data, the proposed methodology is then demonstrated under Vdd=199mV and Vdd=145mV, targeting energy-efficiency priority and Vdd priority scenarios, respectively. This work provides helpful guidelines for FinFET variation-aware near-threshold design.

10:45 AM
28.5 Novel MOS Varactor Device Optimization and Modeling for High-Speed Transceiver Design in FinFET Technology, J. Jing, S. Wu, X. Wu, P. Upadhyaya and A. Bekele, Xilinx Inc.,

For the first time, an optimized MOS varactor design and a new physical based model for advanced FinFET process is presented for high speed analog circuit to achieve high tuning range and low jitter PLL design. The new varactor and model have been validated in 32.75 GB/s high speed transceiver design in 16nm FinFET technology.

11:10 AM
28.6 Embedded Flash Technology for Automotive Applications (Invited), T. Yamauchi, Y. Yamaguchi, T. Kono and H. Hidaka, Renesas Electronics Corporation

Future automotive applications such as advanced driver assistance require further progress of embedded Flash (eFlash) for automotive microcontroller units. Our spilt-gate MONOS eFlash has been successfully scaled down to 28nm process node, because of its excellent reliability and process scalability. Moreover our low-profile SG-MONOS structure enables to integrate with high-K metal gate CMOS for higher performance.