IEDM

Session 27: Memory Technology MRAM

Wednesday, December 7, 9:00 a.m.
Continental Ballroom 4
Co-Chairs: Gwan-Hyeob Koh, Samsung
Hiroki Koike, Tohoku University

9:05 AM
27.1 4Gbit Density STT-MRAM using Perpendicular MTJ Realized with Compact Cell Structure, S.-W. Chung, T. Kishi*, J.W. Park, M. Yoshikawa*, K. S. Park, T. Nagase*, K. Sunouchi*, H. Kanaya*, G.C. Kim, K. Noma*, M. S. Lee, A. Yamamoto*, K. M. Rho*, K. Tsuchida*, S. J. Chung*, J. Y. Yi*, H. S. Kim, Y.S. Chun, H. Oyamatsu* and S. J. Hong, SK Hynix Inc., *Toshiba Electronics Korea Corporation

For the first time, 4Gbit density STT-MRAM using perpendicular MTJ in compact cell was successfully demonstrated. This paper includes the results regarding parasitic resistance control processes, MTJ process, and MTJ stack engineering. Both of successful 4Gb read and write operations were performed with high TMR, low Ic. This result will brighten the prospect of high-density STT-MRAM.

9:30 AM
27.2 Highly Functional and Reliable 8Mb STT-MRAM Embedded in 28nm Logic, Y. J. Song, J. Lee, H.C. Shin, K. H. Lee, K. Suh, J. R. Kang, S. S. Pyo, H. T. Jung, S. H. Hwang, G. H. Koh, S. C. Oh, S. O. Park, J. K. Kim, J. C. Park, J. Kim, K. H. Hwang, G. T. Jeong, K. P. Lee and E. S. Jung, Samsung Electronics Corp.

We fabricated 8Mb 1T-1MTJ STT-MRAM macro embedded in 28nm CMOS logic platform by developing novel integration/stack/patterning technologies. MTJ memory cell array was successfully embedded into Cu backend without open fail and severe degradation of magnetic property. Advanced perpendicular MTJ stack using MgO/CoFeB was developed to show high TMR value of 180% after full integration. In addition, ion beam etching (IBE) process was optimized with power, angle, and pressure to reduce a short fail below 1 ppm. Through these novel technologies, we demonstrated highly functional and reliable 8Mb eMRAM macro having a wide sensing margin and strong retention property of 85 0C and 10yrs.

9:55 AM
27.3 Data Retention Extraction Methodology for Perpendicular STT-MRAM, L. Tillie, E. Nowak, R. Sousa*, M.-C. Cyrille, B. Delaet, T. Magis, A. Persico, J. Langer**, B. Ocker**, I.-L. Prejbeanu* and L. Perniola, CEA-LETI, *SPINTEC, **Singulus Technologies AG

While perpendicular STT-MRAM are seen as a promising next-generation memory, when scaling retention becomes critical and must be characterized precisely. Four extraction methods are compared taking special emphasize on accuracy and precision. They are then applied on single cell to kb-array, from 50 to 250 nm diameter cells and up to 235°C.

10:20 AM
27.4 Systematic Validation of 2x nm Diameter Perpendicular MTJ Arrays and MgO Barrier for Sub-10 nm Embedded STT-MRAM with Practically Unlimited Endurance, J. Kan, C. Park, C. Ching*, J. Ahn*, L. Xue*, R. Wang*, A. Kontos*, S. Liang*, M. Bangar*, H. Chen*, S. Hassan*, S. Kim, M. Pakala* and S. Kang, Qualcomm Technologies, Inc., *Applied Materials, Inc.

We present a comprehensive device and scalability validation of STT-MRAM for high performance applications in sub-10 nm CMOS by providing the first statistical account of barrier reliability in perpendicular magnetic tunnel junctions (pMTJs) from 70 to 25 nm diameter in 1 Gbit arrays. We have experimentally investigated the time- dependent dielectric breakdown (TDDB) properties and the dependence of the pMTJ lifetime on voltage, polarity, duty-cycle, and temperature. A large write-to-breakdown voltage window of > 1 V (> 20 σ_avg) was measured and a long time-to- breakdown was projected (> 10^15 cycles) for 45 nm pMTJs, guaranteeing practically unlimited write cycles. We also reveal a dramatic enhancement of barrier reliability in conjunction with pMTJ size scaling down to 25 nm diameter, further widening the operating window at deeply scaled nodes.

10:45 AM
27.5 Novel Voltage Controlled MRAM (VCM) with Fast Read/Write Circuits for Ultra Large Last Level Cache, H. Noguchi, K. Ikegami, K. Abe, S. Fujita, Y. Shiota*, T. Nozaki*, S. Yuasa* and Y. Suzuki*, Toshiba Corporation, *National Institute of Advanced Industrial Science and Technology

This paper presents voltage-controlled MRAM (VCM) using fast read and write circuits for ultra-large last level cache. Our proposed circuit utilizes unipolar characteristics of voltage-torque MTJ and its voltage effects. The energy barrier is controlled by applying pulsed biases. The proposed VCM can operate even with 10%-sigma variability of fabrication.

11:10 AM
27.6 Voltage-Control Spintronics Memory (VoCSM) Having Potentials of Ultra-Low Energy-Consumption and High-Density, H. Yoda, N. Shimomura, Y. Ohsawa, S. Shirotori, Y. Kato, T. Inokuchi, Y. Kamiguchi, B. Altansargai, Y. Saito, K. Koi, H. Sugiyama, S. Oikawa, M. Shimizu, M. Ishikawa, K. Ikegami and A. Kurobe, Toshiba Corporation

We propose a new spintronics-based memory employing the voltage-control-magnetic-anisotropy effect as a bit selecting principle and the spin-orbit-torque effect as a writing principle. We have fabricated the prototype structure, and successfully demonstrated the writing scheme specific to this memory architecture.