Session 19: Nano Device Technology Tunnel and Nanowire FETs
Tuesday, December 6, 2:15 p.m.
Continental Ballroom 5
Co-Chairs: Rossella Ranica, STMicroelectronics
Andreas Schenk, ETH Zurich
19.1 Vertical InAs/GaAsSb/GaSb Tunneling Field-Effect Transistor on Si with S = 48 mV/decade and Ion = 10 µA/µm for Ioff = 1 nA/µm at VDS = 0.3 V, E. Memisevic, J. Svensson, M. Hellenbrand, E. Lind and L.-E.Wernersson, Lund University
A vertical nanowire InAs/GaAsSb/GaSb TFET, with a Smin of 48 mV/dec. for VDS = 0.1 – 0.5 V and Ion = 10.6 µA/µm for Ioff = 1 nA/µm at VDS = 0.3 V is presented. The TFET demonstrates S<60 mV/decade for IDS=1 nA/µm up to a record high I60=0.31 µA/µm.
19.2 Two-dimensional Heterojunction Interlayer Tunnel FET(Thin-TFET): From Theory to Applications (Invited), M. Li, R. Yan, D. Jena, and G. Xing, Cornell University
We review the conception and development of two-dimensional heterojunction interlayer field effect transistor (Thin-TFET), where a steep subthreshold swing (SS) and a high on-current are estimated theoretically. The Thin-TFET has been experimentally demonstrated using WSe2/SnSe2 stacked heterostructures, where the SS is mostly likely limited by the interfacial trap density of states and the parasitic MOSFET. Due to its vertical stacking structure, Thin-TFET intrinsically has a smaller gate-drain capacitance compared to the conventional lateral pin-TFET. In turn, this results in mitigated Miller Effect in Thin-TFET thus reducing dynamic energy dissipation in circuits.
19.3 Hybrid Phase-Change – Tunnel FET (PC-TFET) Switch with Subthreshold Swing < 10mV/decade and sub-0.1 body Factor: Digital and Analog Benchmarking, E. Casu, W. Vitale, N. Oliva, T. Rosca, C. Alper, A. Biswas, A. Krammer, G. Luong*, S. Mantl*, A. Schuler, A. Seabaugh** and A. Ionescu, EPFL, *Peter Grünberg Institut, **University of Notre Dame
In this paper we report the first hybrid Phase-Change – Tunnel FET (PC-TFET) device configurations for achieving a deep sub-thermionic steep subthreshold swing at room temperature and subthreshold power savings. The proposed hybrid device feedbacks the steep transition of Metal-Insulator transition in a VO2 structure into Gate or Source configurations of strained silicon nanowire Tunnel FETs, to achieve a switching with Ion/Ioff better that 5.5×106 and with a subthreshold swing of 4.0 mV/dec at 25 °C. We demonstrate that the principle of PC-TFET switching relates to an internal amplification resulting in a sub-unity body factor, m, which is reduced to values below 0.1 for a current range larger than 2-3 decades. We report a full experimental digital and analog benchmarking of the new device and compare it with Tunnel FETs and CMOS. Remarkably, the PC-TFET can achieve analog figures of merit like gm/Id breaking the 40 V-1 limit of MOSFETs. We demonstrate and report the first buffered oscillator cell for neuromorphic computing exploiting the gate configuration of PC-TFET.
19.4 Demonstrating Performance Improvement of Complementary TFET Circuits by ION Enhancement Based on Isoelectronic Trap Technology, T. Mori, H. Asai, J. Hattori, K. Fukuda, S. Otsuka, Y. Morita, S. O’uchi, H. Fuketa, S. Migita, W. Mizubayashi, H. Ota and T. Matsukawa, National Institute of Advanced Industrial Science and Technology (AIST)
IET technology, which enhances tunneling probability, successfully increased the ON current in Si-TFETs. The I_ON enhancement improved the inverter and ring oscillator (RO) circuit performance. The RO circuit operation with the complementary TFET inverters was demonstrated for the first time. IET technology may provide a breakthrough towards realizing TFET circuits.
19.5 Tunneling MOSFET Technologies using III-V/Ge Materials (Invited), S. Takagi, D. Ahn, M. Noguchi, T. Gotow, K. Nishi, M. Kim and M. Takenaka, The University of Tokyo
The critical issues, technical challenges and viable technologies of tunneling MOSFETs (TFET) utilizing III-V/Ge materials are examined in this study. N-channel TFETs using InGaAs bulk and quantum well (QW) homo- junctions, GaAsSb/InGaAs and Ge/strained SOI type-II hetero-junction are fabricated with emphasis on the superior source p+/n junction formation and the electrical properties are experimentally evaluated.
19.6 Performance Benchmarking of p-type In0.65Ga0.35As/GaAs0.4Sb0.6 and Ge/Ge0.93Sn0.07 Hetero-junction Tunnel FETs, R. Pandey, C. Schulte-Braucks*, R. N. Sajjad**, M. Barth, R.K. Ghosh*, B. Grisafe*, P. Sharma*, N. von den Driesch***, A. Vohra^, B. Rayner^^, R. Loo^^, S. Mantl***, D. Buca***, C-C. Yeh^^^, C-H. Wu^^^, W. Tsai^^^, D. Antoniadis** and S. Datta*, The Pennsylvania State University, *University of Notre Dame, **Massachusetts Institute of Technology, ***Peter Grünberg Institute (PGI-9) and JARA-FIT, Forschungszentrum Jülich GmbH, ^IMEC, ^^Kurt J. Lesker Company, ^^^Taiwan Semiconductor Manufacturing Company
Experimental demonstration of PTFETs at low |VDS|=0.5V is presented using Group III-V (In0.65Ga0.35As/GaAs0.4Sb0.6) and Group IV (Ge/Ge0.93Sn0.07) semiconductor hetero-junctions exhibiting record minimum switching slope performance. This is enabled by engineering high quality gate stacks on GaAs0.4Sb0.6 and Ge0.88Sn0.12 substrates with thinnest demonstrated EOT of ~ 0.8 nm. Harnessing low direct band gap advantage in Ge1-XSnX PTFETs, together with 10× lower Dit over competing Group III-V In0.65Ga0.35As/GaAs0.4Sb0.6 PTFETs, are excellent candidates for PTFETs with high ION and sub-kT/q SS.
19.7 Vertically Stacked Gate-All-Around Si Nanowire CMOS Transistors with Dual Work Function Metal Gates, H. Mertens,; R. Ritzenthaler, A. Chasin, T. Schram, E. Kunnen, A. Hikavyy, L.-Å. Ragnarsson, H. Dekkers, T. Hopf, K. Wostyn, K. Devriendt, S. A. Chew, M. S. Kim, Y. Kikuchi, E. Rosseel, G. Mannaert, S. Kubicek, S. Demuynck, A. Dangol, N. Bosman, J. Geypen, P. Carolan, H. Bender, K. Barla, N. Horiguchi and D. Mocuta, Imec
We report on the CMOS integration of vertically stacked gate-all-around (GAA) silicon nanowire MOSFETs, with matched threshold voltages (VT,SAT ~ 0.35V) for N- and P-type devices. The VT setting is enabled by nanowire-compatible dual-work-function metal integration in a high-k last replacement metal gate process. Furthermore, we demonstrate that N- and P-type junction formation can influence nanowire release differently due to both implantation-induced SiGe/Si intermixing and doping effects. These findings underline that junction formation and nanowire release require co-optimization in GAA CMOS technologies.