IEDM

Session 17: Process and Manufacturing Technology Silicon Based Advanced CMOS

Tuesday, December 6, 2:15 p.m.
Grand Ballroom A
Co-Chairs: Pierre Morin, STMicroelectronics
Jong-Ho Lee, Seoul National University

2:20 PM
17.1 Air Spacer for 10nm FinFET CMOS and Beyond, K. Cheng, C. Park*, C. W. Yeung, S. Nguyen, J. Zhang, X. Miao, M. Wang, S. Mehta, J. Li, C. Surisetty, R. Muthinti, Z. Liu, H. Tang, S. Tsai*, T. Yamashita, H. Bu and R. Divakaruni, IBM, *GLOBALFOUNDRIES

For the first time, we report integration of air spacers with FinFET technology at 10nm node dimensions. The benefit of parasitic capacitance reduction by air spacers has been successfully demonstrated both at transistor level (15-25% reduction in overlap capacitance (Cov)) and at ring oscillator level (10-15% reduction in effective capacitance (Ceff)). Key process challenges and device implications of integrating air spacers in FinFET are identified. We propose a partial air spacer scheme, in which air spacers are formed only above fin top and sandwiched by two dielectric liners, as a viable option to adopt air spacers in FinFET technology with minimal risks to yield and reliability.

2:45 PM
17.2 FinFET Performance with Si:P and Ge:Group-III-Metal Metastable Contact Trench Alloys, O. Gluschenkov, Z. Liu, H. Niimi*, S. Mochizuki, J. Fronheiser*, X. Miao, J. Li, J. Demarest, C. Zhang, C. Niu*, B. Liu*, A. Petrescu, P. Adusumilli, J. Yang, H. Jagannathan, H. Bu and T. Yamashita, IBM Research at Albany Nanotech, *GLOBALFOUNDRIES Inc.,

We achieved record n-type and p-type S/D contact resistivity of mid-10-10 Ohm-cm2 and 1.9×10-9 Ohm-cm2, respectively, by employing laser-induced liquid or solid phase epitaxy and forming semi-metallic, semiconductor-dopant metastable alloys within nano-scale contact trenches. Correspondingly, large Ron reduction and Id gain have been realized in scaled FinFETs.

3:10 PM
17.3 FOI FinFET with Ultra-low Parasitic Resistance Enabled by Fully Metallic Source and Drain Formation on Isolated Bulk-Fin, Q. Zhang, H. Yin, J. Luo, H. Yang, L. Meng, Y. Li, Z. Wu, Y. Zhang, Y. Zhang, C. Qin, J. Li, J. Gao, G. Wang, W. Xiong, J. Xiang, Z. Zhou, S. Mao, G. Xu, J. Liu, Y. Qu, T. Yang, J. Li, Q. Xu, J. Yan, H. Zhu, C. Zhao and T. Ye, Institute of Microelectronics Chinese Academy of Sciences

The large parasitic resistance has become a critical limiting factor to on current of FinFET and nanowire devices. Fully metallic source and drain (MSD) process is one of the most promising solutions but it often suffers from intolerant junction leakage in bulk FETs. In this paper, fully MSD process on Fin- on-insulator (FOI) FinFET is investigated extensively for the first time. By forming fully Ni(Pt) silicide on FOI FinFET, about 90% reduction in contacted resistivities (Rcs) and 55% reduction in sheet resistances (Rss) are achieved without obvious junction leakage degradation. As a consequence, the on current (ION) of transistor, with gate length (Lg) of 20nm, is increased 30 times, up to 547μA/μm for NMOS and 324 μA/μm for PMOS, respectively. Excellent controls of SCE and channel leakage with 47% DIBL, 32% SS and 2.5% device leakages reductions over the counterpart of conventional bulk FinFETs are also obtained. Meanwhile, the fully MSD process also induces clear tensile stress into narrow fin- channel, resulting in enhanced electron mobility in NMOS. A further improvement in PMOS drive ability (486μA/μm) by using Schottky barrier source and drain (SBSD) technology is also explored.

3:35 PM
17.4 Technology Viable DC Performance Elements for Si/SiGe channel CMOS FinFET, G. Tsutsui, R. Bao, K.-Y. Lim*, R. Robison, R. Vega, J. Yang, Z. Liu, M. Wang, O. Gluschenkov, C. W. Yeung, K. Watanabe, S. Bentley*, H. Niimi*, D. Liu, H. Zhou, S. Siddiqui*, H. Kim*, R. Galatage*, R. Venigalla, M. Raymond*, P. Adusumilli, S. Mochizuki, T. Devarajan, B. Miao, B. Liu*, A. Greene, J. Shearer, P. Montanini, J. Strane, C. Prindle*, E. Miller, J. Fronheiser*, C. Niu*, K. Chung, J. Kelly, H. Jagannathan, S. Kanakasabapathy, G. Karve, F. L. Lie, P. Oldiges, V. Narayanan, T. Hook, A. Knorr*, D. Gupta, D. Guo, R. Divakaruni, H. Bu and M. Khare, IBM Research, *GLOBALFOUNDRIES Inc.

Low Ge content SiGe-based CMOS FinFET is one of the promising technologies offering solutions for both high performance and low power applications. In this paper, we established a competitive SiGe-based CMOS FinFET baseline and examined various elements for high performance offering. The performance elements in gate stack, channel doping, contact resistance, and junction have been explored to provide a cumulative 20% / 25% (n/pFET) performance enhancement. These elements provide a viable path towards performance enhancement for future technology nodes.


4:00 PM
17.5 Improvement of the CMOS Characteristics of Bulk Si FinFETs by High Temperature Ion Implantation, Y. Kikuchi, T. Hopf, G. Mannaert, Z. Tao, A. Waite*, J. Cournoyer*, J. Borniquel*, R. Schreutelkamp*, R. Ritzenthaler, M.-S. Kim, S. Kubicek, S. A. Chew, K. Devriendt, T. Schram, S. Demuynck, N. Variam*, N. Horiguchi and Dan Mocuta, imec, *Applied Materials

For the first time, we established a replacement metal gate CMOS process flow of bulk Si FinFETs for high temperature ion implantation process using dedicated patterning processes on 45-nm fin pitch. A detailed process flow is explained, and better electrical characteristics of MOSFETs and ring oscillators are obtained.

4:25 PM
17.6 Vertically Stacked-NanoWires MOSFETs in a Replacement Metal Gate Process with Inner Spacer and SiGe Source/Drain, S. Barraud, V. Lapras, M.-P. Samson*, L. Gaben*, L. Grenouillet, V. Maffini-Alvaro, Y. Morand*, J. Daranlot, N. Rambal, B. Previtalli, S. Reboh, C. Tabone, R. Coquand, E. Augendre, O. Rozeau, J.-M. Hartmann, C. Vizioz, C. Arvet*, P. Pimenta-Barros, N. Posseme, V. Loup, C. Combotoure*, C. Euvrard, V. Balan, I. Tinti, G. Audoit, N. Bernier, D. Cooper, Z. Saghi, F. Allain, A. Toffoli, O. Faynot and M. Vinet, CEA, LETI, Minatec, *STMicroelectronics

We report on vertically stacked horizontal Si NanoWires (NW) p-MOSFETs fabricated with a replacement metal gate (RMG) process. For the first time, stacked-NWs transistors are integrated with inner spacers and SiGe source-drain (S/D) stressors. Recessed and epitaxially re-grown SiGe(B) S/D junctions are shown to be efficient to inject strain into Si p-channels. The Precession Electron Diffraction (PED) technique, with a nm- scale precision, is used to quantify the deformation and provide useful information about strain fields at different stages of the fabrication process. Finally, a significant compressive strain and excellent short-channel characteristics are demonstrated in stacked-NWs p- FETs

4:50 PM
17.7 A Novel Dual Isolation Scheme for Stress and Back bias Maximum Efficiency in FDSOI Technology, R. Berthelon, F. Andrieu, P. Perreau, D. Cooper, F. Roze, O. Gourhant*, P. Rivallin, N. Bernier, A. Cros*, C. Ndiaye*, E. Baylac*, E. Souchier*, D. Dutartre*, A. Claverie**, O. Weber, E. Josse*, M. Vinet and M. Haond*, CEA-Leti, *STMicroelectronics, **CEMES-CNRS

A novel dual isolation scheme with both Shallow Trench Isolation (STI) and local oxidation, so called Dual Isolation by Trenches and Oxidation (DITO), is presented to maximize the stress induced by SiGe channel and the back biasing efficiency at the same time in FDSOI technology. DITO integration experimentally demonstrates +36% pMOSFET drive current at same leakage, which is translated into -23% ring-oscillator delay reduction at a supply voltage of VDD=0.8V.