Session 15: Characterization, Reliability and Yield FINFET and Nanowire Device Reliability

Tuesday, December 6, 9:00 a.m.
Imperial Ballroom A
Co-Chairs: Anthony Oates, TSMC
Cora Salm, University of Twente

9:05 AM
15.1 Reliability Characterization of 10nm FinFET Technology with multi-VT Gate Stack for Low Power and High Performance, M. J. Jin, C. Liu, J. Kim, J. Kim, H. Shim, K. Kim, G. Kim, S. Lee, T. Uemura, M. Chang#, T. An, J. Park and S. Pae, Samsung Electronics

We report the reliability characterization of 10nm FinFET process technology. Unique reliability behavior by using multi-VT’s through work function engineering is presented. Comparable intrinsic BTI, HCI and TDDB can be achievable vs. 14nm node, while transistors with different VT-types exhibit no extrinsic issues, can support different Vmax. Scaled taller and narrower fin shape increases the transistor self-heating which enhances PMOS HCI and on-state TDDB, yet can be mitigated in realistic circuit operations including AC mode which was further validated with modeling [1]. SRAM and product reliability results including SER also exceeds goal.

9:30 AM
15.2 Consideration of BTI Variability and Product Level Reliability to Expedite Advanced FinFET Process Development (Invited), Y.-H. Lee, J.H. Lee, Y.F. Wang, Roger Hsieh, Y.S. Tsai and K. Huang, TSMC

In this study, the variability of conventional planar (20nm System-on Chip, 20SoC) and FinFET (16nm FinFET, 16FF) time-zero Vt and Bias-Temperature Instability (BTI) induced aging is investigated, as well as its impact on SRAM and Logic product reliability. For 16FF, the Vt after aging is dominated by initial Vt distribution rather than BTI induced Vt shift, and their Vt sigmas are also superior to planar 20SoC. NBTI (Negative Bias Temperature Instability) relaxation between 20SoC and 16FF are comparable, while 16FF shows less PBTI (Positive Bias Temperature Instability) recovery due to the local high field on fin top. Correlation between SRAM static noise margin (SNM) and NBTI induced Vt shift concurs with the domination of initial Vt sigma for SNM drift. Chip and bit level High-Temperature Operating Life (HTOL) burn-in test with recovery phases demonstrates all the recovery occurs right after stress, so there is no Vt mismatch to make more Vmin tailing. Bit level AC and DC HTOL Vmin sigma concurs with the additional Vt mismatch by DC stress. Logic Vmin recovery at higher temperature demonstrates the signature of BTI contribution in Vmin. These results indicate that even some of the BTI features of 16FF are different from 20SoC, the adequate process optimization for initial Vt sigma tightening still dominates SRAM/Logic HTOL Vmin shift rather than BTI aging.

9:55 AM
15.3 Statistical Model of the NBTI-induced Threshold Voltage, Subthreshold Swing, and Transconductance Degradations in Advanced p-FinFETs, J. Franco, B. Kaczer, S. Mukhopadhyay*, P. Duhan*, P. Weckx, P. Roussel, T. Chiarella, L.-Å. Ragnarsson, L. Trojman**, N. Horiguchi, A. Spessot, D. Linten and A. Mocuta, imec, * IIT Bombay, **Universidad San Francisco de Quito

We study the stochastic NBTI degradation of p- FinFETs, in terms of Vth, SS, and gm. We extend our Defect-Centric model to describe also the SS distribution in a population of devices of any area, at any stage of product aging. A large fraction of nanoscale devices is found to show a peak gm improvement after stress. We explain this effect in terms of the interaction of individual defects with the percolative channel conduction, and we propose a statistical description of gm aging. Our Vth, SS, and gm aging models are pluggable into reliability-enabled compact models to estimate design margins for a variety of circuits.

10:20 AM
15.4 Hot Carrier Effect in Ultra-Scaled Replacement Metal Gate Si1-xGex Channel p-FinFETs, M. Wang, X. Miao, Stathis*, R. Southwick, B. Linder*, D. Liu, R. Bao and K. Watanabe, IBM @ Albany Nanotech, *IBM Research Division

Hot carrier reliability is studied in replacement metal gate (RMG) Si1-xGex (x = 20%) channel p-FinFETs with high-k gate dielectrics. In this study, we show that: (1) interface state generation and hole-trapping contribute to the HC damage under high-Vg (~Vd) stress conditions; (2) hot electron injection is the dominant degradation mechanism for low- and mid-Vg biases, which are more representative stress conditions during typical CMOS logic circuit operation. We also found that excessive electron trapping in ultra-scaled SiGe pFinFETs can reduce the effective channel length and significantly increase the off-state leakage current (Ioff).

10:45 AM
15.5 New Understanding of Dielectric Breakdown in Advanced FinFET Devices – Physical, Electrical, Statistical and Multiphysics Study, S. Mei, N. Raghavan, M. Bosman*, D. Linten**, G. Groeseneken**, N. Horiguchi** and K. L. Pey, Singapore University of Technology and Design, *A*STAR, **IMEC
A complete post-mortem study on FinFET dielectric breakdown has been presented combining electro-thermal simulations and reliability test data with in-depth physical analysis insights using TEM/EELS/EDX on multi-fin structures, providing a unified picture. The assumption that the kinetics of failure would remain the same for both planar and FinFET devices is proved to be untrue.

11:10 AM
15.6 Self-heating in FinFET and GAA-NW using Si, Ge and III/V Channels, E. Bury, B. Kaczer, D. Linten, L. Witters, H. Mertens, N. Waldron, X. Zhou, N. Collaert, N. Horiguchi, A. Spessot and G. Groeseneken, IMEC

The self-heating (SH) effect is studied experimentally and through simulations on an extensive set of industry relevant solutions for FF and GAA-NW Si and high-μ devices, with multiple processing options. Considerations for managing SH in future technologies are provided.

11:35 AM
15.7 Substrate and Layout Engineering to Suppress Self-heating in Floating Body Transistors, S.H. Shin, S.H. Kim*, S. K. Kim*, H. Wu, P. D. Ye and M. Alam, Purdue University, *Korea Institute of Science and Technology (KIST)

Self-heating (SH) has emerged as an important performance, variability, and reliability concern for floating body transistors (FB-FET), namely, extremely-thin-silicon-on-insulator (ETSOI), SOI- FinFET, gate-all-round NW-FET (GAA-FETs), etc. The floating body topology offers electrostatic control, but restricts heat outflow: apparently an intrinsic trade-off. In this paper, we trace the trajectory of heat flow in a broad range of transistors to show that the trade-off is not fundamental, and self- heating can be suppressed by novel device designs that ease thermal bottlenecks. Towards this goal, we (i) characterize SH in various FB-FETs with different channel materials (Si, Ge, InGaAs) by submicron thermo-reflectance imaging; (ii) identify universal features and common thermal bottlenecks across various transistor technologies, (iii) offer novel, technology-aware device design to ease the bottlenecks and reduce self-heating, and (iv) experimentally demonstrate the effectiveness of these strategies in suppressing self-heating. We conclude that thermal aware transistor design can suppress self-heating without compromising performance and electrostatic control of the transistor.

12:00 PM
15.8 Local Thermometry of Self-heated Nanoscale Devices (Invited), F. Menges, F. Motzfeld, H. Schmid, P. Mensch, M. Dittberner, S. Karg, H. Riel and B. Gotsmann, IBM Research – Zurich

Hot spots with dimensions of only a few nano¬meters form in numerous nanoelectronic devices. Based on recent advances in spatial resolution, these hotspots can now be studied by means of Scanning Thermal Microscopy (SThM). Here, we discuss SThM for nanoscale thermometry in comparison with other established thermometry techniques. In situ measurements of semiconductor channels for logic, and phase change memory devices are used to demonstrate today’s measurement capabilities. Temperature fields characterize not only energy dissipation in in-tact devices but can also serve to identify device failure and fabrication issues.