Session 13: Optoelectronics, Displays, and Imagers Focus Session: Quantum Computing

Tuesday, December 6, 9:00 a.m.
Continental Ballroom 6
Co-Chairs: Ryoichi Ishihara, QuTech, Delft University of Technology
Michael E. Flatte, University of Iowa

9:05 AM
13.1 Quantum Computing Within the Framework of Advanced Semiconductor Manufacturing (Invited), J.S. Clarke, N. Thomas, J. Roberts, R. Pilliarisetty, Z. Yoscovits, R. Caudillo, H. George, K. J. Singh, D. Michalak, P. Amin, A. Mei, A. Bruno*, S. Poletto*, J. Boter*, G. Droulers*, N. Kalhor*, N. Samkharadze*, J.P. Dehollain*, L. Yeoh*, A. Sammak*, G. Scappucci*, M. Veldhorst*, L. DiCarlo and L. M. K. Vandersypen, Intel Corporation, *TU Delft

Quantum computing holds the promise of exponential speedup compared to classical computing for select algorithms and applications. Relatively small numbers of logical quantum bits or qubits could outperform the largest of supercomputers. Quantum dots in Si-based heterostructures and superconducting Josephson junctions are just two of the many approaches to construct the qubit. These, in particular, bear similarities to the transistors and interconnects used in advanced semiconductor manufacturing. While initial results on few-qubit systems are promising, advanced process control is expected to improve the qubit uniformity, coherence time, and gate fidelity needed for larger systems. This can be realized through the systematic characterization of film growth, interface control, and patterning.

9:30 AM
13.2 Spin-based Quantum Computing in silicon CMOS-compatible Platforms (Invited), A.S. Dzurak, University of South Wales

This paper reviews the current state of development of spin-based quantum bits (qubits) based on silicon metal-oxide-semiconductor (SiMOS) devices, including both single phosphorus donor qubits in silicon and gate-defined quantum dot qubits that are compatible with CMOS manufacturing.

9:55 AM
13.3 Coupled Quantum Dots on SOI as Highly Integrated Si Qubits (Invited), S. Oda, G. Yamahata*, K. Horibe** and T. Kodera, Tokyo Institute of Technology, *NTT Basic Research Laboratories, **Toshiba Corporation

Physically-defined coupled quantum dots (QDs) on silicon-on-insulator substrates represent potential multiple scaled qubits. This work demonstrated the fabrication of coupled QDs with control gates and charge sensor single-electron transistors, the observation of Pauli spin blockade and the control of a few electron regimes, as well as triple QDs and p-channel operation.

10:20 AM
13.4 SOI Technology for Quantum Information Processing(Invited), S. De Franceschi, L. Hutin, R. Maurand, L. Bourdet, H. Bohuslavskyi, A. Corna, D. Kotekar-Patil, S. Barraud, X. Jehl, Y.-M. Niquet, M. Sanquer and M. Vinet, CEA, INAC

We present recent progress towards the implementation of a scalable quantum processor based on fully-depleted silicon-on-insulator (FDSOI) technology. In particular, we discuss an approach where the elementary bits of quantum information – so-called qubits – are encoded in the spin degree of freedom of gate-confined holes in p-type devices. We show how a hole-spin can be efficiently manipulated by means of a microwave excitation applied to the corresponding confining gate. The hole spin state can be read out and reinitialized through a Pauli blockade mechanism. The studied devices are derived from silicon nanowire field-effect transistors. We discuss their prospects for scalability and, more broadly, the potential advantages of FDSOI technology.

10:45 AM
13.5 Cryo-CMOS for Quantum Computing (Invited), E. Charbon, F. Sebastiano, A. Vladimirescu, H. Homulle, S. Visser, L. Song and R. Incandela, Delft University of Technology

Cryogenic CMOS, or cryo-CMOS circuits and systems are emerging in VLSI design for many applications, in primis quantum computing. Fault-tolerant quantum bits (qubits) in surface code configurations, one of the most accepted implementations in quantum computing, operate in deep sub-Kelvin regime and require scalable classical circuits. In this paper we advocate the need of designing a new generation of deep-submicron cryo-CMOS circuits to achieve the performance required in a fault-tolerant qubit system. We outline the challenges and limitations of operating in near-Kelvin regimes, and we propose solutions. The paper concludes with several examples showing the suitability of the proposed approach.

11:10 AM
13.6 Diamond – A Quantum Engineer’s Best Friend (Invited), M. Loncar, Harvard University

11:35 AM
13.7 Large-scale Quantum Technology Based on Luminescent Centers in Crystals (Invited), M. Trupke, C. Salter*, S. Reisenbauer*, R. Vasconcelos, G. Wachter*, K. Buczak*, A. Angerer*, J. Schmiedmayer*, F. Aumayr*, U. Schmid*, P. Walther, W. Munro** and K. Nemoto***, University of Vienna, *Technische Univ. Wien, **Nippon Telegraph and Telephone, ***National Institute of Informatics

Luminescent defects in crystals are prime candidates for the creation of a quantum technology, given their superlative spin coherence lifetimes. Here we describe the main features of a quantum technology based on crystalline defects which builds upon the impressive recent achievements in diamond research. The basic features of the architecture and the requirements for its implementation are outlined, together with experimental progress and practical considerations towards its realization.