IEDM

Session 10: Power Devices Power Semiconductor Device Technologies

Tuesday, December 6, 9:00 a.m.
Continental Ballroom 1-3
Co-Chairs: Srabanti Chowdhury, University of California Davis
Sei-Hyung Ryu, Wolfspeed

9:05 AM
10.1 1.7 kV / 1.0 Ωcm2 Normally-off Vertical GaN Transistor on GaN Substrate with Regrown p-GaN/AlGaN/GaN Semipolar Gate Structure, D. Shibata, R. Kajitani, M. Ogawa, K. Tanaka, S. Tamura, T. Hatsuda, M. Ishida and T. Ueda, Panasonic Corporation

We present a normally-off vertical GaN-based transistor on GaN substrate with low specific on-state resistance of 1.0 mohmcm2 and high breakdown voltage of 1.7 kV. The vertical GaN transistor with p-GaN/AlGaN/GaN semipolar gate structure exhibits high threshold voltage of 2.5V and stable switching operation of 400V/15A.

9:30 AM
10.2 Novel GaN Trench MIS Barrier Schottky Rectifiers with Implanted Field Rings, Y. Zhang, M. Sun, Z. Liu*, D. Piedra, M. Pan**, X. Gao**, Y. Lin, A. Zubair, L. Yu and T. Palacios, Massachusetts Institute of Technology, *Singapore-MIT Alliance for Research Technology, ** IQE RF LLC

We demonstrate a novel GaN vertical Schottky rectifier with trench MIS structures and field rings, for high- voltage and high-frequency applications. The new device greatly enhanced reverse characteristics (10^4-fold lower leakage and 700 V breakdown voltage) while maintaining a good forward conduction, with high- temperature (250 C) operation and fast switching capability.

9:55 AM
10.3 High-Speed Switching and Current-Collapse-Free Operation by GaN Gate Injection Transistors with Thick GaN Buffer on Bulk GaN Substrates, H. Handa, S. Ujita, D. Shibata, R. Kajitani, N. Shiozaki, M. Ogawa, H. Umeda, K. Tanaka, S. Tamura, T. Hatsuda, M. Ishida and T. Ueda, Panasonic Corporation

We present a normally-off Gate Injection transistors (GITs) on GaN substrate. Increasing the thickness of GaN buffer layer greatly helps to reduce output charge enabling fast turn-off switching. The RonQoss as a figure-of-merit for high speed switching is reduced down to 940mohmnC, which leads to high turn-off dV/dt of 285V/ns.

10:20 AM
10.4 Integration of LPCVD-SiNx Gate Dielectric with Recessed-gate E-mode GaN MIS-FETs: Toward High Performance, High Stability and Long TDDB Lifetime, M. Hua, Z. Zhang, J. Wei, J. Lei, G. Tang, K. Fu*, Y. Cai*, B. Zhang* and K. J. Chen, The Hong Kong University of Science and Technology, *Chinese Academy of Sciences

By employing an interface protection technique to prevent the etched GaN surface from degradation during high-temperature process, highly reliable LPCVD-SiNx gate dielectric was successfully integrated with recessed-gate structure to achieve high-performance enhancement-mode GaN MIS-FETs with high Vth thermal stability, long time- dependent gate dielectric breakdown lifetime and low bias temperature instability.

10:45 AM
10.5 Superior Performance of SiC Power Devices and Its Limitation by Self-heating (Invited), T. Terashima, Mitsubishi Electric Corporation

Recently SiC power devices such as SiC-MOSFET have been improved drastically as a next generation power device because of its superior physical property. Although very high carrier density is essential reason for the superior characteristics of that, there is a fundamental problem to realize the predicted performances. One is limit of rating current density by self-heating. The other is destruction by transient self-heating at short circuit event. This paper evaluates performances of SiC-MOSFET compared to Silicon(Si) power devices under the those thermal limitations, and also clarify the substantial requirements to realize the predicted superior performances.

11:10 AM
10.6 Experimental Verification of a 3D Scaling Principle for Low Vce(sat) IGBT, K. Kakushima, T. Hoshii, K. Tsutsui, A. Nakajima*, S. Nishizawa*, H. Wakabayashi, I. Muneta, K. Sato**, T. Matsudai***, W. Saito***, T. Saraya^, K. Itou^, M. Fukui^, S. Suzuki^, M. Kobayashi^, T. Takakura*, T. Hiramoto*, A. Ogura^^, Y. Numasawa^^, I. Omura^^^, H. Ohashi and H. Iwai, Tokyo Institute of Technology, *Nat. Inst. Advanced Industrial Science and Technology, **Mitsubishi Electric Corp., ***Toshiba Corp., ^The University of Tokyo, ^^Meiji University, ^^^Kyushu Institute of Technology

Three dimensionally (3D) scaled IGBTs that have a scaling factor of 3 (k=3) with respect to current commercial products (k=1) were fabricated for the first time. The scaling was applied to the lateral and vertical dimensions as well as the gate voltage. A significant decrease in ON resistance, — Vce(sat) reduction from 1.70 to 1.26 V — was experimentally confirmed for the 3D scaled IGBTs.

11:35 AM
10.7 Experimental Demonstration of -730V Vertical SiC p-MOSFET with High Short Circuit Withstand Capability for Complementary Inverter Applications, J. An, M. Namai, M. Tanabe, D. Okamoto, H. Yano and N. Iwamuro, University of Tsukuba

A new p-channel vertical 4H-SiC MOSFET has been successfully fabricated for the first time. Its breakdown voltage is over -730 V and the short circuit capability is 15% higher than that of 4H-SiC n-channel MOSFET. This could be a superior power device applicable for high frequency complementary inverter.

12:00 PM
10.8 On the Subthreshold Drain Current Sweep Hysteresis of 4H-SiC nMOSFETs, G. Rescher, G. Pobegen, T. Aichinger and T. Grasser, Fellow, IEEE

We study the subthreshold drain current hysteresis of 4H silicon carbide Si-face (0001) and a-face (1120) n-channel power MOSFETs between gate voltage sweeps from accumulation to inversion and vice versa. Depending on the direction of the gate voltage sweep, the MOSFETs show a different subthreshold drain current at the same gate voltage. The observed hysteresis between up-sweep and down-sweep can be expressed as a subthreshold voltage shift and may reach several volts. We show that the voltage shift is caused by hole capture in border traps during accumulation and is directly propotional to the charge pumping signal. The voltage shift is fully recoverable by applying a gate bias above the threshold voltage and does not impact device reliability.