IEDM

2016 IEDM Short Courses

Short Courses provide the opportunity to learn about important areas and developments, and to benefit from direct contact with world experts. Advance registration is recommended.

Short Course #1 Schedule Times

Short Course #2 Schedule Times

Short Course #1: Technology Options at the 5-Nanometer Node
Organizers:  An Steegen, Sr. Vice President of Technology Development, imec and Dan Mocuta, Director of Logic Device and Integration, imec

This course will describe the complex technological challenges at the 5nm node and explore innovative potential solutions. It begins with an in-depth discussion of patterning strategies being pursued to print critical features. Then, a pair of lectures will provide an overview of current transistor technologies and their relative strengths/weaknesses in the context of various applications such as mobility, data centers and IoT. Strategies for effective mitigation of performance-limiting parasitic resistance and capacitance will be discussed, and advanced interconnect technologies including post-copper materials options for BEOL and MEOL applications will be addressed. Lastly, metrology challenges for in-line and end-of-line process technologies will be discussed. The intent of the course is to provide a thorough understanding in process technology targets at the 5nm node and their potential solutions. Attendees will have the opportunity to learn about advanced technology options that are being actively pursued in the industry from leading technologists.

The course consists of lectures from six distinguished speakers:

  • Patterning Technology for 5 nm node, Akihisa Sekiguchi, Corporate VP &  General Manager, Advanced Semiconductor Technology Division, Tokyo Electron Limited, Japan
  • Extending FinFETs to 5nm node, Nadine Collaert, Distinguished Member of the Technical Staff, imec, Belgium
  • Options beyond FinFETs at 5nm node, Aaron Thean, Professor of Electrical & Computer Engineering, National University of Singapore
  • Front-End Parasitic Resistance and Capacitance, Reza Arghavani, Managing Director, Lam Research, USA
  • Back-End Parasitic Resistance and Capacitance Mitigation, Theodorus Standaert, Sr. Engineering Mgr., Manager, Process Integration, and Dan Edelstein, IBM Fellow, IBM, USA
  • Advanced Metrology, Ofer Adan, Technologist and Global Product Manager, Member of the Technical Staff, Applied Materials, Israel

 

Short Course #2: Design/Technology Enablers for Computing Applications
Organizer:  John Chen, Vice President of Technology and Foundry Management, NVIDIA

This course will describe how various design techniques and process technologies can enable computing applications, beginning with the relative advantages and disadvantages of processors such as CPU, GPU and FPGA with regard to today’s high data demands. It then will cover how memory becomes a bottleneck, and will discuss various emerging memory technologies to mitigate the problem. Because managing power dissipation has become critical, it also will offer a broad perspective on power efficiency in computing and how interconnect plays a pivotal role in both performance and energy efficiency. Finally, 2.5-D and 3-D advanced packaging technology is discussed for system integration.

The course consists of lectures from six distinguished speakers:

  • The Rise of Massively Parallel Processing: Why the Demands of Big Data and Power Efficiency are Changing the Computing Landscape, Liam Madden, Corporate VP, Hardware & Systems Development, Xilinx, USA
  • Interconnect Challenges for Computing, William J. Dally, Chief Scientist and Sr. VP of Research, NVIDIA, and Stanford Professor, USA
  • Breaking the Memory Bottleneck in Computing Applications with Emerging Memory Technologies: a Design Perspective (Circuit level), Michel Harrand, Project Manager, CEA-Leti, France
  • Breaking the Memory Bottleneck in Computing Applications with Emerging Memory Technologies: a Technology Perspective (Device level), Gabriel Molas, PhD Engineer, CEA-Leti, France
  • Power Management Integrated Circuits for Computing…and how GaN Changes the Story, Alberto Doronzo, Power System/Apps Engineer, Texas Instruments, USA
  • Advanced Packaging Technologies for System Integration, Douglas Yu, Sr. Director, TSMC, Taiwan